View PD784224Y_5192284.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

78k/iv series 16-bit single chip microcontroller instructions for all 78k/iv series document no. u10905ej7v0um00 (7th edition) date published august 1998 n cp(k) 1997 user? manual printed in japan
2 [memo]
3 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. iebus and qtop are trademarks of nec corporation. ms-dos and windows are either registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at and pc dos are trademarks of international business machines corporation. ethernet is a trademark of xerox corporation. tron is an abbreviation of the realtime operating system nucleus. itron is an abbreviation of industrial tron.
4 caution: purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. the export of these products from japan is regulated by the japanese government. the export of some or all of these products may be prohibited without governmental license. to export or re-export some or all of these products from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. the information in this document is subject to change without notice. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated quality assurance program for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m7 96.5
5 major revisions in this edition pages contents throughout ? addition of m pd784937, 784955 subseries. deletion of m pd784943 subseries. ? the status of following products changed from under development to completed: m pd784031(a), 784035(a), 784036(a), m pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2), m pd784054(a), 784054(a1), 784054(a2), m pd784214, 784214y, m pd784915b, 784916b, m pd784927, 78f4928, 784927y, 78f4928y ? modification of the package from gc-7ea to gc-8eu in m pd78f4216 and 78f4216y. ? modification of the power supply voltage in m pd784908 subseries. mask rom version ( m pd784907, 784908): v dd = 4.5 to 5.5 v ? v dd = 3.5 to 5.5 v prom version ( m pd78p4908): v dd = 4.5 to 5.5 v ? v dd = 3.5 to 5.5 v p. 163 chapter 6 instruction set modification of notes for special instructions (chkl and chkla). p. 291 chapter 7 description of instructions modification of the operation sequences in the pop instruction. addition of caution to the chkl instruction. addition of caution to the chkla instruction. p. 473 chapter 8 development tool modification of arrangement p. 479 chapter 9 software for embedding addition of description regarding pc environment. the mark h shows major revised points.
6 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division rodovia presidente dutra, km 214 07210-902-guarulhos-sp brasil tel: 55-11-6465-6810 fax: 55-11-6465-6829 j98. 8
7 introduction readers : this manual is intended for engineers who understand the functions of 78k/iv series products and wish to design 78k/iv series application systems. ? 78k/iv series products ? m pd784026 subseries : m pd784020, 784021, 784025, 784026, 78p4026 ? m pd784038 subseries : m pd784031, 784035, 784036, 784037, 784038, 78p4038, 784031(a), 784035(a), 784036(a) ? m pd784038y subseries : m pd784031y, 784035y, 784036y, 784037y, 784038y, 78p4038y ? m pd784046 subseries : m pd784044, 784046, 784054, 78f4046, 78444(a), (a1), (a2), m pd784046(a), (a1), (a2), 784054(a), (a1), (a2) ? m pd784216 subseries : m pd784214, 784215, 784216, 78f4216 note ? m pd784216y subseries : m pd784214y, 784215y, 784216y, 78f4216y note ? m pd784218 subseries note : m pd784217, 784218, 78f4218 ? m pd784218y subseries note : m pd784217y, 784218y, 78f4218y ? m pd784225 subseries note : m pd784224, 784225, 78f4225 ? m pd784225y subseries note : m PD784224Y, 784225y, 78f4225y ? m pd784908 subseries note : m pd784907, 784908, 78p4908 ? m pd784915 subseries : m pd784915, 784915a, 784916a, 784915b, 784916b, 78p4916 ? m pd784928 subseries : m pd784927, 78f4928 ? m pd784928y subseries : m pd784927y, 78f4928y ? m pd784937 subseries note : m pd784935, 784936, 784937, 78f4937 ? m pd784955 subseries note : m pd784953, 784955, 78f4956 note under development purpose : the purpose of this manual is to explain the various instruction functions of the 78k/iv series. organization : this manual is broadly organized as follows: ? features of 78k/iv series products ? cpu functions ? instruction set ? instruction descriptions ? development tools
8 how to read this manual : readers require a general understanding of electrical and logic circuits and micro- controllers. ? to check the details of an instruction function when the mnemonic is known: ? use appendix a and appendix b index of instructions . ? to check an instruction when you know the general function but do not know the mnemonic: ? find the mnemonic in chapter 6 instruction set , then check the function in chapter 7 description of instructions . ? for a general understanding of the various instruction functions of the 78k/iv series: ? read in accordance with the contents. ? for information on the hardware functions of the 78k/iv series: ? read the separate users manual. C m pd784026 subseries users manual C hardware (u10898e) C m pd784038/784038y subseries users manual C hardware (u r316e) C m pd784046 subseries users manual C hardware (u11515e) C m pd784054 users manual C hardware (u11719e) C m pd784216/784216y subseries users manual C hardware (u12015e) C m pd784218/784218y subseries users manual C hardware (u12970e) C m pd784225/784225y subseries users manual C hardware (u12679e) C m pd784908 subseries users manual C hardware (u11787e) C m pd784915 subseries users manual C hardware (u10444e) C m pd784928/784928y subseries users manual C hardware (u12648e) C m pd784937 subseries users manual C hardware (to be prepared) C m pd784955 subseries users manual C hardware (u12833e) conventions : significance in data notation : high-order digit on left, low-order digit on right active-low notation : (line above pin or signal name) note : footnote for item marked with note in the text caution : information requiring particular attention remark : supplementary information numeric notations : binary ............... b or decimal ............. hexadecimal ..... h
9 related documents the related documents indicated in this publication may include preliminary versions. however, preliminary versions are not marked as such. ? documents common to the 78k/iv series document name document number japanese english pamphlet u10752j C users manual C instructions u10905j this manual instruction set u10595j instruction list u10594j application note C software basics u10095j u10095e ? individual documents ? m pd784026 subseries document name document number japanese english m pd784020/784021 data sheet u11514j u11514e m pd784025/784026 data sheet u11605j u11605e m pd78p4026 data sheet u11609j u11609e m pd784026 subseries users manual C hardware u10898j u10898e m pd784026 subseries special function register table u10593j m pd784026 subseries application note C hardware basics u10573j u10573e ? m pd784038/784038y subseries document name document number japanese english m pd784031 data sheet u11507j u11507e m pd784035/784036/784037/784038 data sheet u10847j u10847e m pd784031(a) data sheet u13009j u13009e m pd784035(a)/784036(a) data sheet u13010j u13010e m pd78p4038 data sheet u10848j u10848e m pd784038 subseries special function register table u11090j m pd784031y data sheet u11504j u11504e m pd784035y/784036y/784037y/784038y data sheet u10741j u10741e m pd78p4038y data sheet u10742j u10742e m pd784038y subseries special function register table u11091j m pd784038/784038y subseries users manual C hardware u11316j u11316e m pd784038/784038y subseries application note C hardware basics u13285j
10 ? m pd784046 subseries document name document number japanese english m pd784044/784046 data sheet u10951j u10951e m pd784044(a)/784046(a) data sheet u13121j u13121e m pd784054 data sheet u11154j u11154e m pd784054(a) data sheet u13122j u13122e m pd78f4046 preliminary product information u11447j u11447e m pd784046 subseries special function register table u10986j m pd784054 special function register table u11113j m pd784046 subseries users manual C hardware u11515j u11515e m pd784054 users manual C hardware u11719j u11719e ? m pd784216, 784216y subseries document name document number japanese english m pd784214/784215/784216 preliminary product information u11813j u11813e m pd78f4216 preliminary product information u11825j u11825e m pd784216 subseries special function register table u12045j m pd784214y/784215y/784216y preliminary product information u11725j u11725e m pd78f4216y preliminary product information u11824j u11824e m pd784216y subseries special function register table u12046j m pd784216/784216y subseries users manual C hardware u12015j u12015e ? m pd784218, 784218y subseries document name document number japanese english m pd784217/784218 preliminary product information u12303j u12303e m pd78f4218 preliminary product information u12439j u12439e m pd784218 subseries special function register table planned m pd784217y/784218y preliminary product information u12304j u12304e m pd78f4218y preliminary product information u12440j u12440e m pd784218y subseries special function register table u12919j m pd784218/784218y subseries users manual C hardware u12970j u12970e
11 ? m pd784225, 784225y subseries document name document number japanese english m pd784224/784225 preliminary product information u12498j u12498e m pd78f4225 preliminary product information u12499j u12499e m pd784225 subseries special function register table u12689j m PD784224Y/784225y preliminary product information u12376j u12376e m pd78f4225y preliminary product information u12377j u12377e m pd784225y subseries special function register table u12699j m pd784225/784225y subseries users manual C hardware u12679j u12679e ? m pd784908 subseries document name document number japanese english m pd784907/784908 preliminary product information u11680j u11680e m pd78p4908 preliminary product information u11681j u11681e m pd784908 subseries special function register table u11589j m pd784908 subseries users manual C hardware u11787j u11787e ? m pd784915 subseries document name document number japanese english m pd784915 data sheet u11044j u11044e m pd784915a/784916a data sheet u11022j u11022e m pd784915b/784916b data sheet u13118j u13118e m pd78p4916 data sheet u11045j u11045e m pd784915 subseries special function register table u10976j m pd784915 subseries users manual C hardware u10444j u10444e m pd784915 subseries application note C vcr servo basics u11361j u11361e ? m pd784928, 784928y subseries document name document number japanese english m pd784927 data sheet u12255j u12255e m pd78f4928 preliminary product information u12188j u12188e m pd784928 subseries special function register table u11045j m pd784927y data sheet u12373j u12373e m pd78f4928y preliminary product information u12271j u12271e m pd784928y subseries special function register table u12719j m pd784928/784928y subseries users manual C hardware u12648j u12648e
12 ? m pd784937 subseries document name document number japanese english m pd784935/784936/784937 preliminary product information u13572j to be prepared m pd78f4937 preliminary product information u13573j to be prepared m pd784937 subseries special function register table to be prepared m pd784937 subseries users manual C hardware to be prepared to be prepared ? m pd784955 subseries document name document number japanese english m pd784953/784955 preliminary product information u12830j u12830e m pd78f4956 preliminary product information u12831j u12831e m pd784955 subseries special function register table u12832j m pd784955 subseries users manual C hardware u12833j u12833e
13 contents chapter 1 features of 78k/iv series products ............................................................ 21 1.1 78k/iv series product development diagram ................................................................ 23 1.2 product outline of m pd784026 subseries ( m pd784020, 784021, 784025, 784026, 78p4026) ............................................................ 24 1.2.1 features .................................................................................................................. ............. 24 1.2.2 applications .............................................................................................................. ........... 24 1.2.3 ordering information and quality grade ............................................................................... 25 1.2.4 outline of functions ...................................................................................................... ........ 26 1.2.5 block diagram ............................................................................................................. ......... 27 1.3 product outline of m pd784038 subseries ( m pd784031, 784035, 784036, 784037, 784038, 78p4038, 784031(a), 784035(a), 784036(a)) ....................................... 28 1.3.1 features .................................................................................................................. ............. 28 1.3.2 applications .............................................................................................................. ........... 29 1.3.3 ordering information and quality grade ............................................................................... 29 1.3.4 outline of functions ...................................................................................................... ........ 31 1.3.5 block diagram ............................................................................................................. ......... 32 1.4 product outline of m pd784038y subseries ( m pd784031y, 784035y, 784036y, 784037y, 784038y, 78p4038y) .................................. 33 1.4.1 features .................................................................................................................. ............. 33 1.4.2 applications .............................................................................................................. ........... 34 1.4.3 ordering information and quality grade ............................................................................... 34 1.4.4 outline of functions ...................................................................................................... ........ 36 1.4.5 block diagram ............................................................................................................. ......... 37 1.5 product outline of m pd784046 subseries ( m pd784044, 784054, 784046, 78f4046, 784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2), 784054(a), 784054(a1), 784054(a2)) ................................................................................ 38 1.5.1 features .................................................................................................................. ............. 38 1.5.2 applications .............................................................................................................. ........... 38 1.5.3 ordering information and quality grade ............................................................................... 39 1.5.4 outline of functions ...................................................................................................... ........ 40 1.5.5 block diagram ............................................................................................................. ......... 42 1.6 product outline of m pd784216 subseries ( m pd784214, 784215, 784216, 78f4216) .... 44 1.6.1 features .................................................................................................................. ............. 44 1.6.2 applications .............................................................................................................. ........... 44 1.6.3 ordering information and quality grade ............................................................................... 45 1.6.4 outline of functions ...................................................................................................... ........ 46 1.6.5 block diagram ............................................................................................................. ......... 48 1.7 product outline of m pd784216y subseries ( m pd784214y, 784215y, 784216y, 78f4216y) .................................................................. 49 1.7.1 features .................................................................................................................. ............. 49 1.7.2 applications .............................................................................................................. ........... 49 1.7.3 ordering information and quality grade ............................................................................... 50 1.7.4 outline of functions ...................................................................................................... ........ 51 1.7.5 block diagram ............................................................................................................. ......... 53
14 1.8 product outline of m pd784218 subseries ( m pd784217, 784218, 78f4218) .................. 54 1.8.1 features .................................................................................................................. ............. 54 1.8.2 applications .............................................................................................................. ........... 55 1.8.3 ordering information and quality grade ............................................................................... 55 1.8.4 outline of functions ...................................................................................................... ........ 56 1.8.5 block diagram ............................................................................................................. ......... 58 1.9 product outline of m pd784218y subseries ( m pd784217y, 784218y, 78f4218y) ......... 59 1.9.1 features .................................................................................................................. ............. 59 1.9.2 applications .............................................................................................................. ........... 60 1.9.3 ordering information and quality grade ............................................................................... 60 1.9.4 outline of functions ...................................................................................................... ........ 61 1.9.5 block diagram ............................................................................................................. ......... 63 1.10 product outline of m pd784225 subseries ( m pd784224, 784225, 78f4225) .................. 64 1.10.1 features ................................................................................................................. .............. 64 1.10.2 applications ............................................................................................................. ............ 65 1.10.3 ordering information and quality grade ............................................................................... 65 1.10.4 outline of functions ..................................................................................................... ......... 66 1.10.5 block diagram ............................................................................................................ .......... 68 1.11 product outline of m pd784225y subseries ( m PD784224Y, 784225y, 78f4225y) ......... 69 1.11.1 features ................................................................................................................. .............. 69 1.11.2 applications ............................................................................................................. ............ 70 1.11.3 ordering information and quality grade ............................................................................... 70 1.11.4 outline of functions ..................................................................................................... ......... 71 1.11.5 block diagram ............................................................................................................ .......... 73 1.12 product outline of m pd784908 subseries ( m pd784907, 784908, 78p4908) ................. 74 1.12.1 features ................................................................................................................. .............. 74 1.12.2 applications ............................................................................................................. ............ 75 1.12.3 ordering information and quality grade ............................................................................... 75 1.12.4 outline of functions ..................................................................................................... ......... 76 1.12.5 block diagram ............................................................................................................ .......... 78 1.13 product outline of m pd784915 subseries ( m pd784915, 784915a, 784916a, 784915b, 784916b, 78p4916) .................................... 79 1.13.1 features ................................................................................................................. .............. 79 1.13.2 applications ............................................................................................................. ............ 79 1.13.3 ordering information and quality grade ............................................................................... 80 1.13.4 outline of functions ..................................................................................................... ......... 81 1.13.5 block diagram ............................................................................................................ .......... 82 1.14 product outline of m pd784928 subseries ( m pd784927, 78f4928) ................................ 83 1.14.1 features ................................................................................................................. .............. 83 1.14.2 applications ............................................................................................................. ............ 83 1.14.3 ordering information ..................................................................................................... ....... 84 1.14.4 outline of functions ..................................................................................................... ......... 85 1.14.5 block diagram ............................................................................................................ .......... 86 1.15 product outline of m pd784928y subseries ( m pd784927y, 78f4928y) ......................... 87 1.15.1 features ................................................................................................................. .............. 87 1.15.2 applications ............................................................................................................. ............ 87 1.15.3 ordering information ..................................................................................................... ....... 88 1.15.4 outline of functions ..................................................................................................... ......... 89 1.15.5 block diagram ............................................................................................................ .......... 90
15 1.16 product outline of m pd784937 subseries ( m pd784935, 784936, 78f4937, 78f4937) . 91 1.16.1 features ................................................................................................................. .............. 91 1.16.2 applications ............................................................................................................. ............ 91 1.16.3 ordering information and quality grade ............................................................................... 92 1.16.4 outline of functions ..................................................................................................... ......... 93 1.16.5 block diagram ............................................................................................................ .......... 95 1.17 product outline of m pd784955 subseries ( m pd784953, 784955, 78f4956) .................. 96 1.17.1 features ................................................................................................................. .............. 96 1.17.2 applications ............................................................................................................. ............ 96 1.17.3 ordering information and quality grade ............................................................................... 97 1.17.4 outline of functions ..................................................................................................... ......... 98 1.17.5 block diagram ............................................................................................................ .......... 100 chapter 2 memory space ....................................................................................................... 101 2.1 memory space ................................................................................................................ ... 101 2.2 internal rom area ........................................................................................................... .. 103 2.3 base area ................................................................................................................... ....... 105 2.3.1 vector table area ......................................................................................................... ........ 106 2.3.2 callt instruction table area .............................................................................................. . 106 2.3.3 callf instruction entry area .............................................................................................. . 106 2.4 internal data area .......................................................................................................... ... 107 2.4.1 internal ram area ......................................................................................................... ...... 107 2.4.2 special function register (sfr) area ................................................................................... 112 2.4.3 external sfr area ......................................................................................................... ...... 112 2.5 external memory space ................................................................................................... 112 chapter 3 registers ............................................................................................................. ... 113 3.1 control registers ........................................................................................................... ... 113 3.1.1 program counter (pc) ...................................................................................................... ... 113 3.1.2 program status word (psw) ................................................................................................ 1 13 3.1.3 use of rss bit ............................................................................................................ ......... 117 3.1.4 stack pointer (sp) ........................................................................................................ ....... 121 3.2 general registers ........................................................................................................... .. 125 3.2.1 configuration ............................................................................................................. .......... 125 3.2.2 functions ................................................................................................................. ............ 127 3.3 special function registers (sfr) ................................................................................... 130 chapter 4 interrupt functions .......................................................................................... 131 4.1 kinds of interrupt request ............................................................................................... 132 4.1.1 software interrupt requests ............................................................................................... .. 132 4.1.2 non-maskable interrupt requests ........................................................................................ 132 4.1.3 maskable interrupt requests ............................................................................................... . 132 4.2 interrupt service modes ................................................................................................... 13 3 4.2.1 vectored interrupts ....................................................................................................... ....... 133 4.2.2 context switching ......................................................................................................... ....... 133 4.2.3 macro service function .................................................................................................... ..... 134
16 chapter 5 addressing ............................................................................................................ 135 5.1 instruction address addressing ..................................................................................... 135 5.1.1 relative addressing ....................................................................................................... ...... 136 5.1.2 immediate addressing ...................................................................................................... ... 137 5.1.3 table indirect addressing ................................................................................................. .... 139 5.1.4 16-bit register addressing ................................................................................................ .... 140 5.1.5 20-bit register addressing ................................................................................................ .... 140 5.1.6 16-bit register indirect addressing ....................................................................................... 141 5.1.7 20-bit register indirect addressing ....................................................................................... 142 5.2 operand address addressing ......................................................................................... 143 5.2.1 implied addressing ........................................................................................................ ...... 144 5.2.2 register addressing ....................................................................................................... ...... 145 5.2.3 immediate addressing ...................................................................................................... ... 146 5.2.4 8-bit direct addressing ................................................................................................... ...... 147 5.2.5 16-bit direct addressing .................................................................................................. ..... 148 5.2.6 24-bit direct addressing .................................................................................................. ..... 149 5.2.7 short direct addressing ................................................................................................... ..... 150 5.2.8 special function register (sfr) addressing function ........................................................... 152 5.2.9 short direct 16-bit memory indirect addressing ................................................................... 153 5.2.10 short direct 24-bit memory indirect addressing ................................................................... 154 5.2.11 stack addressing ......................................................................................................... ........ 155 5.2.12 24-bit register indirect addressing ...................................................................................... . 156 5.2.13 16-bit register indirect addressing ...................................................................................... . 158 5.2.14 based addressing ......................................................................................................... ....... 159 5.2.15 indexed addressing ....................................................................................................... ...... 160 5.2.16 based indexed addressing ................................................................................................. . 161 chapter 6 instruction set .................................................................................................... 163 6.1 legend ...................................................................................................................... ......... 163 6.2 list of instruction operations .......................................................................................... 167 6.3 instructions listed by type of addressing .................................................................... 193 6.4 operation codes ............................................................................................................. .. 198 6.4.1 operation code symbols .................................................................................................... .. 198 6.4.2 list of operation codes ................................................................................................... ..... 201 6.5 number of instruction clocks .......................................................................................... 259 6.5.1 execution time of instruction ............................................................................................. ... 259 6.5.2 legend for clocks column ................................................................................................ . 259 6.5.3 explanation of clocks column ........................................................................................... 2 60 6.5.4 list of number of clocks .................................................................................................. ..... 261 chapter 7 description of instructions .......................................................................... 291 7.1 8-bit data transfer instruction ......................................................................................... 293 7.2 16-bit data transfer instruction ....................................................................................... 296 7.3 24-bit data transfer instruction ....................................................................................... 299 7.4 8-bit data exchange instruction ...................................................................................... 301 7.5 16-bit data exchange instruction .................................................................................... 303 7.6 8-bit operation instructions ............................................................................................. 305 7.7 16-bit operation instructions ........................................................................................... 315
17 7.8 24-bit operation instructions ........................................................................................... 322 7.9 multiplication/division instructions ................................................................................ 325 7.10 special operation instructions ........................................................................................ 331 7.11 increment/decrement instructions .................................................................................. 341 7.12 adjustment instructions ................................................................................................... 3 48 7.13 shift/rotate instructions .................................................................................................. 352 7.14 bit manipulation instructions .......................................................................................... 363 7.15 stack manipulation instructions ...................................................................................... 374 7.16 call/return instructions ................................................................................................... 386 7.17 unconditional branch instruction ................................................................................... 400 7.18 conditional branch instructions ..................................................................................... 402 7.19 cpu control instructions ................................................................................................. 42 2 7.20 special instructions ....................................................................................................... ... 432 7.21 string instructions ........................................................................................................ .... 435 chapter 8 development tools ............................................................................................ 473 8.1 development tools ........................................................................................................... 474 8.2 prom programming tools .............................................................................................. 477 8.3 flash memory programming tools ................................................................................. 478 chapter 9 embedded software .......................................................................................... 479 9.1 real-time os ................................................................................................................ ...... 479 appendix a index of instructions (mnemonics: by function) .................................. 481 appendix b index of instructions (mnemonics: alphabetical order) ................ 485 appendix c revision history .................................................................................................. 4 87
18 1-1. 78k series and 78k/iv series composition ....................................................................... 22 2-1. memory map ................................................................................................................. ...... 102 2-2. internal ram memory mapping .......................................................................................... 110 3-1. program counter (pc) configuration ................................................................................. 113 3-2. program status word (psw) configuration ....................................................................... 114 3-3. stack pointer (sp) configuration ....................................................................................... 121 3-4. data saved to stack area .................................................................................................. 1 22 3-5. data restored from stack area .......................................................................................... 123 3-6. general register configuration .......................................................................................... 125 3-7. general register addresses .............................................................................................. 126 4-1. context switching operation by interrupt request generation ......................................... 133 8-1. development tools structure ............................................................................................. 476 list of figures figure no. title page
19 list of tables table no. title page 2-1. list of internal rom space for 78k/iv series products ..................................................... 103 2-2. vector table ............................................................................................................... ......... 106 2-3. internal ram area in 78k/iv series products .................................................................... 108 3-1. register bank selection .................................................................................................... .116 3-2. function names and absolute names ............................................................................... 129 4-1. interrupt request servicing ................................................................................................ 131 6-1. list of instructions by 8-bit addressing .............................................................................. 193 6-2. list of instructions by 16-bit addressing ............................................................................ 194 6-3. list of instructions by 24-bit addressing ............................................................................ 195 6-4. list of instructions by bit manipulation instruction addressing ........................................... 196 6-5. list of instructions by call/return instruction/branch instruction addressing .................... 197 8-1. types and functions of development tools ....................................................................... 474
20 [memo]
21 chapter 1 features of 78k/iv series products the 78k series consists of 6 series as shown in figure 1-1. the 78k/iv series is one of these 6 series, comprising products with an on-chip 16-bit cpu. these products have an instruction set suitable for control applications, a high-performance interrupt controller, and incorporate a high-performance cpu equipped with a maximum 1-mbyte program memory space and maximum 16-mbyte data memory space. the 78k/iv series offers a variety of subseries, enabling the most suitable subseries to be selected for a particular application. all the subseries have the same cpu, and differ only in their peripheral hardware. consequently, the entire instruction set is common to all subseries. moreover, individual products within a subseries differ only in the size of on-chip memory.
22 chapter 1 features of 78k/iv series products figure 1-1. 78k series and 78k/iv series composition 78k series 78k/0s series 78k/0 series 78k/i series 78k/ii series 78k/iii series 78k/iv series 8-bit single-chip microcontrollers m pd784038 subseries m pd784038y subseries m pd784046 subseries m pd784216 subseries m pd784026 subseries 16-bit single-chip microcontrollers m m m m m m pd784216y subseries m m pd784218 subseries m m pd784218y subseries m m pd784225 subseries m m pd784225y subseries m m pd784908 subseries m m pd784915 subseries m m pd784928 subseries m m pd784928y subseries m m pd784937 subseries m m pd784955 subseries m
23 chapter 1 features of 78k/iv series products 1.1 78k/iv series product development diagram pd784026 pd784038y i 2 c bus supported pd784038 enhanced internal memory capacity, pin compatible with the pd784026 pd784225y multimaster i 2 c bus supported pd784225 80 pins, added rom correction pd784218y multimaster i 2 c bus supported multimaster i 2 c bus supported pd784218 enhanced internal memory capacity, added rom correction pd784928y multimaster i 2 c bus supported pd784928 enhanced function of the pd784915 pd784216y pd784054 pd784216 pd784046 on-chip 10-bit a/d 100 pins, enhanced i/o and internal memory capacity enhanced a/d, 16-bit timer, and power management pd784915 equipped with analog circuit for sofware servo control vcr, enhanced timer standard models assp models : under mass production : under development m m m m m m m m m m m m m m m m pd784908 on-chip iebus tm controller m pd784955 for dc inverter control m m pd784937 enhanced function of the pd784908, enhanced internal memory capacity, added rom correction m
24 chapter 1 features of 78k/iv series products 1.2 product outline of m pd784026 subseries ( m pd784020, 784021, 784025, 784026, 78p4026) 1.2.1 features ? pins are compatible with m pd78234 subseries ? minimum instruction execution time: 160 ns/320 ns/640 ns/1,280 ns (at 25-mhz operation) ? on-chip memory ? rom mask rom : 48 kbytes ( m pd784025) 64 kbytes ( m pd784026) none ( m pd784020, 784021) prom : 64 kbytes ( m pd78p4026) ? ram : 2,048 bytes ( m pd784021, 784025, 784026) 512 bytes ( m pd784020) ? i/o pins: 64 46 ( m pd784020, 784021 only) ? timer/counter: 16-bit timer/counter 3 units 16-bit timer 1 unit ? watchdog timer: 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, sbi): 1 channel ? interrupt controller (4-level priority) vectored interrupt/macro service/context switching ? standby function: halt/stop/idle mode ? clock output function selectable from f clk , f clk /2, f clk /4, f clk /8, f clk /16 (except m pd784020, 784021) ? power supply voltage: v dd = 2.7 to 5.5 v 1.2.2 applications laser beam printers, autofocus cameras, plain paper copiers, printers, electronic typewriters, air conditioners, electronic musical instruments, cellular phones, etc.
25 chapter 1 features of 78k/iv series products 1.2.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784020gc-3b9 80-pin plastic qfp (14 14 mm) none m pd784021gc-3b9 80-pin plastic qfp (14 14 mm) none m pd784021gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) none m pd784025gc- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784026gc- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd78p4026gc-3b9 80-pin plastic qfp (14 14 mm) one-time prom m pd78p4026gc- -3b9 note 80-pin plastic qfp (14 14 mm) preprogramming one-time prom m pd78p4026kk-t 80-pin ceramic wqfn (14 14 mm) eprom note qtop tm microcontroller. qtop microcontroller is a general term for a single-chip microcontroller with on-chip one-time prom, for which total support is provided by nec programming service, from programming to marking, screening, and verification. remark indicates rom code suffix. (2) quality grades part number package quality grade m pd784020gc-3b9 80-pin plastic qfp (14 14 mm) standard m pd784021gc-3b9 80-pin plastic qfp (14 14 mm) standard m pd784021gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784025gc- -3b9 80-pin plastic qfp (14 14 mm) standard m pd784026gc- -3b9 80-pin plastic qfp (14 14 mm) standard m pd78p4026gc-3b9 80-pin plastic qfp (14 14 mm) standard m pd78p4026gc- -3b9 note 80-pin plastic qfp (14 14 mm) standard m pd78p4026kk-t 80-pin ceramic wqfn (14 14 mm) not applicable (for function evaluation) note qtop microcontroller. qtop microcontroller is a general term for a single-chip microcontroller with on-chip one-time prom, for which total support is provided by nec programming service from programming to marking, screening, and verification. please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. caution the eprom version of the m pd78p4026 does not have a level of reliability intended for volume production of customers equipment, and should only be used for experimental or preproduction function evaluation. remark indicates rom code suffix.
26 chapter 1 features of 78k/iv series products number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) minimum instruction execution time 160 ns/320 ns/640 ns/1,280 ns (at 25-mhz operation) internal memory capacity none 48 kbytes 64 kbytes 64 kbytes (mask rom) (mask rom) (prom) ram 512 bytes 2,048 bytes memory space 1 mbyte total both program and data i/o port total 46 64 input 8 8 input/output 34 56 output 4 0 pin with pull-up resistor 32 54 led direct drive output 8 24 transistor direct drive 8 real-time output port 4 bits 2, or 8 bits 1 timer/counter timer/counter 0: timer register 1 pulse output capability (16-bit) compare register 2 ? toggle output capture register 1 ? pwm/ppg output ? one-shot pulse output timer/counter 1: timer register 1 pulse output capability (8-/16-bit) compare register 1 ? real-time output: 4 bits 2 capture register 1 capture/compare register 1 timer/counter 2: timer register 1 pulse output capability (8-/16-bit) compare register 1 ? toggle output capture/compare register 1 ? pwm/ppg output capture register 1 timer 3: timer register 1 (8-/16-bit) compare register 1 watchdog timer 1 channel pwm output function 12-bit resolution 2 channels serial interface ? uart ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o, sbi) : 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels standby function halt/stop/idle mode interrupt hardware sources 23 (internal: 16, external: 7 (sampling clock variable input: 1) ) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 15, external: 6 ? 4-level programmable priority ? 3 kinds of process mode (vectored interrupt/macro service/context switching) clock output function selectable from f clk , f clk /2, f clk /4, f clk /8, f clk /16 (also usable as 1-bit output port) power supply voltage v dd = 2.7 to 5.5 v package ? 80-pin plastic qfp (14 14 mm) ? 80-pin plastic tqfp (fine pitch, 12 12 mm: m pd784021 only) ? 80-pin ceramic wqfn (14 14 mm: m pd78p4026 only) 1.2.4 outline of functions product name m pd784020 m pd784021 m pd784025 m pd784026 m pd78p4026 item rom additional function pin note note the pins with additional functions are included in the i/o pins.
27 chapter 1 features of 78k/iv series products 1.2.5 block diagram nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 ani0 to ani7 av dd av ref1 av ss intp5 programmable interrupt controller timer/ counter0 (16 bits) timer/ counter1 (16 bits) timer/ counter2 (16 bits) pwm a/d converter d/a converter real-time output port timer3 (16 bits) 78k/iv cpu core rom ram watchdog timer uart/ioe2 baud-rate generator uart/ioe1 baud-rate generator clocked serial interface clock output bus i/f port0 port1 port2 port3 port4 port5 port6 port7 system control r x d/si1 t x d/so1 asck/sck1 r x d2/si2 t x d2/so2 asck2/sck2 sck0 so0/sb0 si0 astb/clkout ad0 to ad7 a8 to a15 reset a16 to a19 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 test x1 x2 v pp v dd v ss d0 to d7 (a0 to a16) (ce) (oe) (pgm) remarks 1. internal rom and ram capacities vary depending on the products. 2. v pp applies to the m pd78p4026 only. 3. the pins in parentheses are used in the prom programming mode.
28 chapter 1 features of 78k/iv series products 1.3 product outline of m pd784038 subseries ( m pd784031, 784035, 784036, 784037, 784038, 78p4038, 784031(a), 784035(a), 784036(a)) 1.3.1 features ? pins are compatible with m pd78234 subseries, m pd784026 subseries, and m pd784038y subseries ? on-chip memory capacity of m pd78234 subseries and m pd784026 subseries is expanded. ? minimum instruction execution time 125 ns/250 ns/500 ns/1,000 ns (at 32-mhz operation) ? on-chip memory ? rom mask rom : none ( m pd784031, 784031(a)) 48 kbytes ( m pd784035, 784035(a)) 64 kbytes ( m pd784036, 784036(a)) 96 kbytes ( m pd784037) 128 kbytes ( m pd784038) prom : 128 kbytes ( m pd78p4038) ? ram : 2,048 bytes ( m pd784031, 784035, 784036, 784031(a), 784035(a), 784036(a)) 3,584 bytes ( m pd784037) 4,352 bytes ( m pd784038) ? i/o port: 64 ? timer/counter: 16-bit timer/counter 3 units 16-bit timer 1 unit ? watchdog timer: 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? 12-bit pwm output: 2 channels ? serial interface uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o, 2-wire serial i/o): 1 channel ? interrupt controller (4-level priority) vectored interrupt/macro service/context switching ? standby function halt/stop/idle mode ? clock output function selectable from f clk , f clk /2, f clk /4, f clk /8, and f clk /16 (except m pd784031) ? power supply voltage: v dd = 2.7 to 5.5 v
29 chapter 1 features of 78k/iv series products 1.3.2 applications ? standard-grade devices: laser beam printers, autofocus cameras, plain paper copiers, printers, electronic typewriters, air conditioners, electronic musical instruments, cellular phones, etc. ? special-grade devices: control equipment in automobile electrical system, gas detector and cut off equipment, and various safety equipment. 1.3.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784031gc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) none m pd784031gc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) none m pd784031gc(a)- -3e9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) none m pd784031gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) none m pd784035gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784035gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784035gc(a)- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784035gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784036gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784036gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784036gc(a)- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784036gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784037gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784037gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784037gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784038gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784038gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784038gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd78p4038gc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) one-time prom m pd78p4038gc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) one-time prom m pd78p4038gc- -3b9 note 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) preprogramming one-time prom m pd78p4038gc- -8bt note 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) preprogramming one-time prom m pd78p4038gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) one-time prom m pd78p4038gk- -be9 note 80-pin plastic tqfp (fine pitch) (12 12 mm) preprogramming one-time prom m pd78p4038kk-t 80-pin ceramic wqfn (14 14 mm) eprom note qtop microcontrollers. qtop microcontroller is a general term for a single-chip microcontroller with on- chip one-time rom, for which total support is provided by nec programming service, from programming to marking, screening, and verification. remark indicates rom code suffix.
30 chapter 1 features of 78k/iv series products (2) quality grades part number package quality grade m pd784031gc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784031gc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784031gc-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784035gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784035gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784035gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784036gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784036gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784036gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784037gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784037gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784037gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784038gc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784038gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784038gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78p4038gc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd78p4038gc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd78p4038gc- -3b9 note 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd78p4038gc- -8bt note 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd78p4038gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78p4038gk- -be9 note 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784031gc(a)- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) special m pd784035gc(a)- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) special m pd784036gc(a)- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) special m pd78p4038kk-t 80-pin ceramic wqfn (14 14 mm) not applicable (for function evaluation) note qtop microcontrollers. qtop microcontroller is a general term for a single-chip microcontroller with on- chip one-time rom, for which total support is provided by nec programming service, from programming to marking, screening, and verification. please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the eprom version of the m pd78p4028 does not have a level of reliability intended for volume production of customers equipment, and should only be used for experimental or preproduction function evaluation.
31 chapter 1 features of 78k/iv series products 1.3.4 outline of functions product name m pd784031, m pd784035, m pd784036, m pd784037 m pd784038 m pd78p4038 item 784031(a) 784035(a) 784036(a) number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) minimum instruction execution time 125 ns/250 ns/500 ns/1,000 ns (at 32-mhz operation) internal memory capacity rom none 48 kbytes 64 kbytes 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (mask rom) (mask rom) (one-time prom or eprom) ram 2,048 bytes 3,584 bytes 4,352 bytes memory space 1 mbyte total both programs and data i/o port total 64 input 8 input/output 56 pin with pull-up resistor 54 led direct drive output 24 transistor direct drive 8 real-time output port 4 bits 2, or 8 bits 1 timer/counter timer/counter 0: timer register 1 pulse output capability (16-bit) capture register 1 ? toggle output compare register 2 ? pwm/ppg output ? one-shot pulse output timer/counter 1: timer register 1 pulse output capability (8/16-bit) capture register 1 ? real-time output (4 bits 2) capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability (8/16-bit) capture register 1 ? toggle output capture/compare register 1 ? pwm/ppg output compare register 1 timer 3: timer register 1 (8/16-bit) compare register 1 pwm output 12-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f clk , f clk /2, f clk /4, f clk /8, and f clk /16 (also usable as 1-bit output port) watchdog timer 1 channel standby function halt/stop/idle mode interrupt hardware sources 23 (internal: 16, external: 7 (sampling clock variable input: 1) ) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 15, external: 6 ? 4-level programmable priority ? 3 processing modes (vectored interrupt, macro service, context switching) power supply voltage v dd = 2.7 to 5.5 v package ? 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) ? 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin ceramic wqfn (14 14 mm): m pd78p4038 only note the pins with additional functions are included in the i/o pins. additional function pin note
32 chapter 1 features of 78k/iv series products 1.3.5 block diagram nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 ani0 to ani7 av av ref1 av ss intp5 programmable interrupt controller timer/ counter0 (16 bits) timer/ counter1 (16 bits) timer/ counter2 (16 bits) pwm a/d converter d/a converter real-time output port timer3 (16 bits) 78k/iv cpu core rom ram watchdog timer uart/ioe2 baud-rate generator uart/ioe1 baud-rate generator clocked serial interface clock output bus i/f port0 port1 port2 port3 port4 port5 port6 port7 system control r x d/si1 t x d/so1 asck/sck1 r x d2/si2 t x d2/so2 asck2/sck2 sck0/scl so0/sda si0 astb/clkout ad0 to ad7 a8 to a15 reset a16 to a19 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 test x1 x2 v pp v dd v ss d0 to d7 (a0 to a16) (ce) (oe) (pgm) remarks 1. internal rom and ram capacities vary depending on the products. 2. v pp applies to the m pd78p4038 only. 3. the pins in parentheses are used in the prom programming mode
33 chapter 1 features of 78k/iv series products 1.4 product outline of m pd784038y subseries ( m pd784031y, 784035y, 784036y, 784037y, 784038y, 78p4038y) 1.4.1 features ? i 2 c bus control function is added to m pd784038. ? pins are compatible with m pd78234 subseries, m pd784026 subseries, and m pd784038. ? on-chip memory capacity of m pd78234 subseries and m pd784026 subseries is expanded. ? minimum instruction execution time: 125 ns/250 ns/500 ns/1,000 ns (at 32-mhz operation) ? on-chip memory ? rom mask rom : none ( m pd784031y) 48 kbytes ( m pd784035y) 64 kbytes ( m pd784036y) 96 kbytes ( m pd784037y) 128 kbytes ( m pd784038y) prom : 128 kbytes ( m pd78p4038y) ? ram : 2,048 bytes ( m pd784031y, 784035y, 784036y) 3,584 bytes ( m pd784037y) 4,352 bytes ( m pd784038y) ? i/o port: 64 ? timer/counter: 16-bit timer/counter 3 units 16-bit timer 1 unit ? watchdog timer: 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? 12-bit pwm output: 2 channels ? serial interface uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus): 1 channel ? interrupt controller (4-level priority) vectored interrupt/macro service/context switching ? standby function halt/stop/idle modes ? clock output function selectable from f clk , f clk /2, f clk /4, f clk /8,and f clk /16 (except m pd784031y) ? power supply voltage: v dd = 2.7 to 5.5 v
34 chapter 1 features of 78k/iv series products 1.4.2 applications cellular phones, cordless phones, audiovisual equipment, etc. 1.4.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784031ygc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) none m pd784031ygc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) none m pd784031ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) none m pd784035ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784035ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784035ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784036ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784036ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784036ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784037ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784037ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784037ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784038ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) mask rom m pd784038ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) mask rom m pd784038ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd78p4038ygc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) one-time prom m pd78p4038ygc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) one-time prom m pd78p4038ygc- -3b9 note 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) preprogramming one-time prom m pd78p4038ygc- -8bt note 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) preprogramming one-time prom m pd78p4038ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) one-time prom m pd78p4038ygk- -be9 note 80-pin plastic tqfp (fine pitch) (12 12 mm) preprogramming one-time prom m pd78p4038ykk-t 80-pin ceramic wqfn (14 14 mm) eprom note qtop microcontrollers. qtop microcontroller is a general term for a single-chip microcontroller with on- chip one-time rom, for which total support is provided by nec programming service, from programming to marking, screening, and verification. remark indicates rom code suffix. caution m pd784035ygk- -be9 and m pd784036ygk- -be9 are under development.
35 chapter 1 features of 78k/iv series products (2) quality grades part number package quality grade m pd784031ygc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784031ygc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784031ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784035ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784035ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784035ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784036ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784036ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784036ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784037ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784037ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784037ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784038ygc- -3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd784038ygc- -8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd784038ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78p4038ygc-3b9 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd78p4038ygc-8bt 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd78p4038ygc- -3b9 note 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) standard m pd78p4038ygc- -8bt note 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) standard m pd78p4038ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78p4038ygk- -be9 note 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78p4038ykk-t 80-pin ceramic wqfn (14 14 mm) not applicable (for function evaluation) note qtop microcontrollers. qtop microcontroller is a general term for a single-chip microcontroller with on- chip one-time rom, for which total support is provided by nec programming service, from programming to marking, screening, and verification. please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. cautions 1. the eprom version of the m pd78p4028 dose not have a level of reliability intended for volume production of customers equipment, and should only be used for experimental or preproduction function evaluation. 2. m pd784035ygk- -be9 and m pd784036ygk- -be9 are under development.
36 chapter 1 features of 78k/iv series products 1.4.4 outline of functions product name m pd784031y m pd784035y m pd784036y m pd784037y m pd784038y m pd78p4038y item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) minimum instruction execution time 125 ns/250 ns/500 ns/1,000 ns (at 32-mhz operation) internal memory capacity rom none 48 kbytes 64 kbytes 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (mask rom) (mask rom) (one-time prom or eprom) ram 2,048 bytes 3,584 bytes 4,352 bytes memory space 1 mbyte total both programs and data i/o port total 64 input 8 input/output 56 pin with pull-up resistor 54 led direct drive output 24 transistor direct drive 8 real-time output port 4 bits 2, or 8 bits 1 timer/counter timer/counter 0: timer register 1 pulse output capability capture register 1 ? toggle output compare register 2 ? pwm/ppg output ? one-shot pulse output timer/counter 1: timer register 1 pulse output capability capture register 1 ? real-time output (4 bits 2) capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability capture register 1 ? toggle output capture/compare register 1 ? pwm/ppg output compare register 1 timer 3: timer register 1 compare register 1 pwm output 12-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o, i 2 c bus) : 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f clk , f clk /2, f clk /4, f clk /8,and f clk /16 (also usable as 1-bit output port) watchdog timer 1 channel standby function halt/stop/idle mode interrupt hardware sources 24 (internal: 17, external: 7 (sampling clock variable input: 1) ) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 16, external: 6 ? 4-level programmable priority ? 3 processing modes (vectored interrupt, macro service, context switching) power supply voltage v dd = 2.7 to 5.5 v package ? 80-pin plastic qfp (14 14 mm, thickness: 1.4 mm) ? 80-pin plastic qfp (14 14 mm, thickness: 2.7 mm) ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin ceramic wqfn (14 14 mm): m pd78p4038y only note the pins with additional functions are included in the i/o pins. additional function pin note
37 chapter 1 features of 78k/iv series products 1.4.5 block diagram nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 ani0 to ani7 av dd av ref1 av ss intp5 programmable interrupt controller timer/ counter0 (16 bits) timer/ counter1 (16 bits) timer/ counter2 (16 bits) pwm a/d converter d/a converter real-time output port timer3 (16 bits) 78k/iv cpu core rom ram watchdog timer uart/ioe2 baud-rate generator uart/ioe1 baud-rate generator clocked serial interface clock output bus i/f port0 port1 port2 port3 port4 port5 port6 port7 system control r x d/si1 t x d/so1 asck/sck1 r x d2/si2 t x d2/so2 asck2/sck2 sck0/scl so0/sda si0 astb/clkout ad0 to ad7 a8 to a15 reset a16 to a19 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 test x1 x2 v pp v dd v ss d0 to d7 (a0 to a16) (ce) (oe) (pgm) remarks 1. internal rom and ram capacities vary depending on the products. 2. v pp applies to the m pd78p4038y only. 3. the pins in parenthesis are used in the prom programming mode.
38 chapter 1 features of 78k/iv series products 1.5 product outline of m pd784046 subseries ( m pd784044, 784054, 784046, 78f4046, 784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2), 784054(a), 784054(a1), 784054(a2)) 1.5.1 features ? minimum instruction execution time: 125 ns (at internal 16-mhz operation) .......... m pd784044, 784046, 784054, 78f4046 160 ns (at internal 12.5-mhz operation) ....... m pd784044(a), 784046(a), 784054(a) 200 ns (at internal 10-mhz operation) .......... m pd784044(a1), (a2), 784046(a1), (a2), 784054(a1), (a2) ? on-chip memory ? rom mask rom : 64 kbytes ( m pd784046, 784046(a), (a1), (a2)) : 32 kbytes ( m pd784044, 784044(a), (a1), (a2), 784054, 784054(a), (a1), (a2)) flash memory : 64 kbytes ( m pd78f4046) ? ram : 2,048 bytes ( m pd784046, 784046(a), (a1), (a2), 78f4046) 1,024 bytes ( m pd784044, 784044(a), (a1), (a2), 784054, 784054(a), (a1), (a2)) ? i/o port: 65 (64 for only m pd784054 and 784054(a), (a1), (a2)) ? timer/counter: 16-bit timer/counter 2 units 16-bit timer 3 units (only 16-bit timer 3 units for m pd784054 and 784054(a), (a1), (a2)) ? watchdog timer: 1 channel ? a/d converter: 10-bit resolution 16 channels (v dd = 4.5 to 5.5 v) ? serial interface uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) ? interrupt controller (4-level priority) vectored interrupt/macro service/context switching ? standby function halt/stop/idle mode (/standby invalid function mode m pd784054 and 784054(a), (a1), (a2) only) ? power supply voltage: v dd = 4.0 to 5.5 v 1.5.2 applications ? standard: water heaters, vending machines, office automation equipment such as ppcs or printers, and factory automation equipment such as robots or automation machine tools ? special: automobile electrical systems, etc.
39 chapter 1 features of 78k/iv series products 1.5.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784044gc- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784044gc(a)- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784044gc(a1)- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784044gc(a2)- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784046gc- -3b9 note 80-pin plastic qfp (14 14 mm) mask rom m pd784046gc(a)- -3b9 note 80-pin plastic qfp (14 14 mm) mask rom m pd784046gc(a1)- -3b9 note 80-pin plastic qfp (14 14 mm) mask rom m pd784046gc(a2)- -3b9 note 80-pin plastic qfp (14 14 mm) mask rom m pd784054gc- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784054gc(a)- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784054gc(a1)- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd784054gc(a2)- -3b9 80-pin plastic qfp (14 14 mm) mask rom m pd78f4046gc-3b9 note 80-pin plastic qfp (14 14 mm) flash memory remark indicates rom code suffix. (2) quality grades part number package quality grade m pd784044gc- -3b9 80-pin plastic qfp (14 14 mm) standard m pd784046gc- -3b9 note 80-pin plastic qfp (14 14 mm) standard m pd784054gc- -3b9 80-pin plastic qfp (14 14 mm) standard m pd78f4046gc-3b9 note 80-pin plastic qfp (14 14 mm) standard m pd784044gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special m pd784044gc(a1)- -3b9 80-pin plastic qfp (14 14 mm) special m pd784044gc(a2)- -3b9 80-pin plastic qfp (14 14 mm) special m pd784046gc(a)- -3b9 note 80-pin plastic qfp (14 14 mm) special m pd784046gc(a1)- -3b9 note 80-pin plastic qfp (14 14 mm) special m pd784046gc(a2)- -3b9 note 80-pin plastic qfp (14 14 mm) special m pd784054gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special m pd784054gc(a1)- -3b9 80-pin plastic qfp (14 14 mm) special m pd784054gc(a2)- -3b9 80-pin plastic qfp (14 14 mm) special please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. note under development remark indicates rom code suffix.
40 chapter 1 features of 78k/iv series products 1.5.4 outline of functions (1) m pd784044, 784044(a), (a1), (a2), 784046, 784046(a), (a1), (a2), 78f4046 product name m pd784044, m pd784046, m pd78f4046 item 784044(a), (a1), (a2) 784046(a), (a1), (a2) number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) minimum instruction execution time 125 ns (at internal clock 16-mhz operation) ..... m pd784044, 78f4046 160 ns (at internal clock 12.5-mhz operation) .. m pd784044(a), 784046(a) 200 ns (at internal clock 10-mhz operation) ..... m pd784044(a1), (a2), 784046(a1), (a2) on-chip memory capacity rom 32 kbytes 64 kbytes 64 kbytes (mask rom) (mask rom) (flash memory) ram 1,024 bytes 2,048 bytes memory space 1 mbyte total both programs and data i/o port total 65 input 17 input/output 48 pin with pull-up resistor 29 real-time output port 4 bits 1 timer/counter timer 0: timer register 1 pulse output capability capture/compare register 4 ? toggle output ? set/reset output timer 1: timer register 1 pulse output capability compare register 2 ? toggle output ? set/reset output timer/counter 2: timer register 1 pulse output capability compare register 2 ? toggle output ? pwm/ppg output timer/counter 3: timer register 1 pulse output capability compare register 2 ? toggle output ? pwm/ppg output timer 4: timer register 1 pulse output capability compare register 2? real-time output (4 bits 1) a/d converter 10-bit resolution 16 channels (av dd = 4.5 to 5.5 v) serial interface uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) watchdog timer 1 channel interrupt hardware sources 27 (internal: 23, external: 8 (compatible with internal: 4)) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 22, external: 7 (compatible with internal: 4) ? 4-level programmable priority ? 3 processing modes (vectored interrupt, macro service, context switching) bus sizing function 8-bit/16-bit external data bus selectable standby function halt/stop/idle mode power supply voltage v dd = 4.0 to 5.5 v package 80-pin plastic qfp (14 14 mm) note the pins with additional functions are included in the i/o pins. additional function pin note
41 chapter 1 features of 78k/iv series products (2) m pd784054, 784054(a), (a1), (a2) product name m pd784054, 784054(a), (a1), (a2) item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) minimum instruction execution time 125 ns (at internal clock 16-mhz operation) ...... m pd784054 160 ns (at internal clock 12.5-mhz operation) ... m pd784054(a) 200 ns (at internal clock 10-mhz operation) ...... m pd784054(a1), (a2) on-chip memory capacity 32 kbytes (mask rom) ram 1,024 bytes memory space 1 mbyte total both programs and data i/o port total 64 input 17 input/output 47 pin with pull-up resistor 29 timer timer 0: timer register 1 pulse output capability (16-bit) capture/compare register 4 ? toggle output ? set/reset output timer 1: timer register 1 pulse output capability (16-bit) compare register 2 ? toggle output ? set/reset output timer 4: timer register 1 (16-bit) compare register 2 a/d converter 10-bit resolution 16 channels (av dd = 4.5 to 5.5 v) serial interface uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) watchdog timer 1 channel interrupt hardware sources 23 (internal: 19, external: 8 (compatible with internal: 4)) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 18, external: 7 (compatible with internal: 4) ? 4-level programmable priority ? 3 processing modes (vectored interrupt, macro service, context switching) bus sizing function 8-bit/16-bit external data bus selectable standby function halt/stop/idle mode/standby invalid function mode power supply voltage v dd = 4.0 to 5.5 v package 80-pin plastic qfp (14 14 mm) note the pins with additional functions are included in the i/o pins. rom additional function pin note
42 chapter 1 features of 78k/iv series products 1.5.5 block diagram (1) m pd784044, 784044(a), (a1), (a2), 784046, 784046(a), (a1), (a2), 78f4046 nmi intp0 to intp6 intp0 to intp3 to00 to to03 to10, to11 intp5/ti2 to20, to21 intp6/ti3 to30, to31 rtp0 to rtp3 intp4 av ref av ss av dd ani0 to ani15 watchdog timer a/d converter real-time output port timer4 (16 bits) timer/counter3 (16 bits) timer/counter2 (16 bits) timer1 (16 bits) timer0 (16 bits) programmable interrupt controller 78k/iv cpu core rom ram uart/ioe1 baud-rate generator uart/ioe2 baud-rate generator bus i/f port0 port1 port2 port3 port4 port5 port6 port7 port8 port9 system control v dd v ss reset mode x1 x2 v pp note p90 to p94 p80 to p87 p70 to p77 p60 to p63 p50 to p57 p40 to p47 p30 to p37 p10 to p13 p00 to p03 p21 to p27 p20 bwd ad0 to ad15 a16 to a19 rd lwr, hwr astb wait rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 clkout note v pp applies to the m pd78f4046 only. remark internal rom and ram capacities vary depending on the products.
43 chapter 1 features of 78k/iv series products (2) m pd784054, 784054(a), (a1), (a2) nmi intp0 to intp6 intp0 to intp3 to00 to to03 to10, to11 intp4 av ref av ss av dd ani0 to ani15 watchdog timer a/d converter timer4 (16 bits) timer1 (16 bits) timer0 (16 bits) programmable interrupt controller 78k/iv cpu core rom ram uart/ioe1 baud-rate generator uart/ioe2 baud-rate generator bus i/f system control v dd v ss reset mode mode1 x1 x2 port9 p90 to p94 port8 p80 to p87 port7 p70 to p77 port6 p60 to p63 port5 p50 to p57 port4 p40 to p47 port3 p30 to p37 port1 p10 to p13 port0 p00 to p03 port2 p21 to p27 p20 bwd ad0 to ad15 a16 to a19 rd lwr, hwr astb wait rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 clkout
44 chapter 1 features of 78k/iv series products 1.6 product outline of m pd784216 subseries ( m pd784214, 784215, 784216, 78f4216) 1.6.1 features ? peripheral functions of m pd78078 are inherited ? minimum instruction execution time: 160 ns (at 12.5-mhz main system clock operation) 61 m s (at 32.768-khz subsystem clock operation) ? on-chip memory ? rom mask rom : 96 kbytes ( m pd784214) 128 kbytes ( m pd784215, 784216) flash memory : 128 kbytes ( m pd78f4216) ? ram : 3,584 bytes ( m pd784214) : 5,120 bytes ( m pd784215) 4,352 bytes ( m pd784216, 78f4216) ? i/o port : 86 ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 6 units ? watch timer: 1 channel ? watchdog timer: 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o): 1 channel ? interrupt controller (4-level priority) vectored interrupt/macro service/context switching ? clock output function selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt ? buzzer output function selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 ? standby function halt/stop/idle mode low power consumption mode: halt/idle mode (subsystem clock operation) ? power supply voltage: v dd = 1.8 to 5.5 v 1.6.2 applications cellular phones, phs, cordless phones, cd-roms, audiovisual equipment, etc.
45 chapter 1 features of 78k/iv series products 1.6.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784214gc- -8eu 100-pin plastic lqfp (fine pitch) mask rom (14 14 mm) m pd784214gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784215gc- -8eu 100-pin plastic lqfp (fine pitch) mask rom (14 14 mm) m pd784215gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784216gc- -8eu 100-pin plastic lqfp (fine pitch) mask rom (14 14 mm) m pd784216gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4216gc-8eu 100-pin plastic lqfp (fine pitch) flash memory (14 14 mm) m pd78f4216gf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. caution m pd78f4216gc-8eu and m pd78f4216gf-3ba are under development. (2) quality grades part number package quality grade m pd784214gc- -8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd784214gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784215gc- -8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd784215gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784216gc- -8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd784216gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4216gc-8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd78f4216gf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution m pd78f4216gc-8eu and m pd78f4216gf-3ba are under development.
46 chapter 1 features of 78k/iv series products 1.6.4 outline of functions product name m pd784214 m pd784215 m pd784216 m pd78f4216 item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) 160 n/320 ns/640 ns/1,280 ns/2,560 ns (at 12.5-mhz operation) 61 m s (at 32.768-khz operation) internal memory capacity 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (flash memory) ram 3,584 bytes 5,120 bytes 8,192 bytes memory space 1 mbyte total both programs and data i/o port total 86 cmos input 2 cmos i/o 72 n-ch open-drain 6 i/o additional pin with pull-up 70 function pin note resistor led direct drive output 22 medium voltage 6 resistance pin real-time output port 4 bits 2, or 8 bits 1 timer/counter 16-bit timer/counter: timer register 1 pulse output capability capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output 8-bit timer/counter 1: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 2: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 5: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 6: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 7: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 8: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output note the pins with additional functions are included in the i/o pins. minimum instruction execution time when main system clock is selected when subsystem clock is selected rom (1/2)
47 chapter 1 features of 78k/iv series products product name m pd784214 m pd784215 m pd784216 m pd78f4216 item a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (baud rate generator on-chip) csi (3-wire serial i/o): 1 channel clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel interrupt hardware sources 29 (internal: 20, external: 9) software sources brk instruction, brkcs instructions, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 8 ? 4-level programmable priority ? 3 processing modes: vectored interrupt, macro service, context switching standby function ? halt/stop/idle mode ? low power consumption mode (cpu can operate on subsystem clock): halt/idle mode power supply voltage v dd = 1.8 to 5.5 v package ? 100-pin plastic lqfp (fine pitch) (14 14 mm) ? 100-pin plastic qfp (14 20 mm) (2/2)
48 chapter 1 features of 78k/iv series products 1.6.5 block diagram intp2/nmi intp0,intp1, intp3 to intp6 programmable interrupt controller real-time output port timer/counter 7 (8 bits) timer/counter 8 (8 bits) timer/counter6 (8 bits) timer/counter5 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 ti5/to5 ti6/to6 ti7/to7 ti8/to8 rtp0 to rtp7 clock output control a/d converter av ss av dd pcl buzzer output buz av ref0 ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface si0 so0 sck0 bus i/f rd astb wr wait a0 to a7 ad0 to ad7 a8 to a15 a16 to a19 port0 p00 to p06 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port8 p80 to p87 port9 p90 to p95 port10 p100 to p103 port12 p120 to p127 port13 p130,p131 system control reset xt2 x1 xt1 x2 v ss v dd test/v pp note note v pp applies to the m pd78f4216 only. remark internal rom and ram capacities vary depending on the products.
49 chapter 1 features of 78k/iv series products 1.7 product outline of m pd784216y subseries ( m pd784214y, 784215y, 784216y, 78f4216y) 1.7.1 features ? i 2 c bus interface is added to m pd784216 subseries ? minimum instruction execution time: 160 ns (main system clock: at 12.5-mhz operation) 61 m s (subsystem clock: at 32.768-khz operation) ? on-chip memory ? rom mask rom : 96 kbytes ( m pd784214y) 128 kbytes ( m pd784215y, 784216y) flash memory : 128 kbytes ( m pd78f4216y) ? ram : 3,584 bytes ( m pd784214y) 5,120 bytes ( m pd784215y) 8,192 bytes ( m pd784216y, 78f4216y) ? i/o port: 86 ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 6 units ? watch timer: 1 channel ? watchdog timer: 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o, multimaster supported i 2 c bus): 1 channel ? interrupt controller (4-level priority) vectored interrupt/macro service/context switching ? clock output functions selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt ? buzzer output functions selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 ? standby function halt/stop/idle mode low power consumption mode: halt/idle mode (subsystem clock operation) ? power supply voltage: v dd = 1.8 to 5.5 v 1.7.2 applications cellular phones, phs, cordless phones, cd-roms, audiovisual equipment, etc.
50 chapter 1 features of 78k/iv series products 1.7.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784214ygc- -8eu 100-pin plastic lqfp (fine pitch) mask rom (14 14 mm) m pd784214ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784215ygc- -8eu 100-pin plastic lqfp (fine pitch) mask rom (14 14 mm) m pd784215ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784216ygc- -8eu 100-pin plastic lqfp (fine pitch) mask rom (14 14 mm) m pd784216ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4216ygc-8eu 100-pin plastic lqfp (fine pitch) flash memory (14 14 mm) m pd78f4216ygf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. caution m pd78f4216ygc-8eu and m pd78f4216ygf-3ba are under development. (2) quality grades part number package quality grade m pd784214ygc- -8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd784214ygf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784215ygc- -8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd784215ygf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784216ygc- -8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd784216ygf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4216ygc-8eu 100-pin plastic lqfp (fine pitch) standard (14 14 mm) m pd78f4216ygf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution m pd78f4216ygc-8eu and m pd78f4216ygf-3ba are under development.
51 chapter 1 features of 78k/iv series products 1.7.4 outline of functions product name m pd784214y m pd784215y m pd784216y m pd78f4216y item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (12.5-mhz operation) 61 m s (32.768-khz) internal memory capacity 96 kbytes 128 kbytes 128 kbytes (mask rom) (mask rom) (flash memory) ram 3,584 bytes 5,120 bytes 8,192 bytes memory space 1 mbyte total both programs and data i/o port total 86 cmos input 2 cmos i/o 72 n-ch open-drain 6 i/o additional pin with pull-up 70 function pin note resistor led direct drive output 22 medium voltage 6 resistance pin real-time output port 4 bits 2, or 8 bits 1 timer/counter 16-bit timer/counter: timer register 1 pulse output capability capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output 8-bit timer/counter 1: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 2: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 5: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 6: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 7: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output 8-bit timer/counter 8: timer register 1 pulse output capability compare register 1 ? pwm output ? square wave output a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels note the pins with additional functions are included in the i/o pins. minimum instruction execution time when main system clock is selected when subsystem clock is selected rom (1/2)
52 chapter 1 features of 78k/iv series products product name m pd784214y m pd784215y m pd784216y m pd78f4216y item serial interface ? uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o, multimaster supported i 2 c bus): 1 channel clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel interrupt hardware sources 29 (internal: 20, external: 9) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 8 ? 4-level programmable priority ? 3 processing modes: vectored interrupt, macro service, context switching standby function ? halt/stop/idle mode ? low power consumption mode (cpu can operate on subsystem clock): halt/idle mode power supply voltage v dd = 1.8 to 5.5 v package ? 100-pin plastic lqfp (fine pitch) (14 14 mm) ? 100-pin plastic qfp (14 20 mm) (2/2)
53 chapter 1 features of 78k/iv series products 1.7.5 block diagram intp2/nmi intp0,intp1, intp3 to intp6 programmable interrupt controller real-time output port timer/counter 7 (8 bits) timer/counter 8 (8 bits) timer/counter6 (8 bits) timer/counter5 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 ti5/to5 ti6/to6 ti7/to7 ti8/to8 rtp0 to rtp7 clock output control a/d converter av ss av dd pcl buzzer output buz av ref0 ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface si0/sda0 so0 sck0/scl0 bus i/f rd astb wr wait a0 to a7 ad0 to ad7 a8 to a15 a16 to a19 port0 p00 to p06 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port8 p80 to p87 port9 p90 to p95 port10 p100 to p103 port12 p120 to p127 port13 p130,p131 system control reset xt2 x1 xt1 x2 v ss v dd test/v pp note note v pp applies to the m pd78f4216y only. remark internal rom and ram capacities vary depending on the products.
54 chapter 1 features of 78k/iv series products 1.8 product outline of m pd784218 subseries ( m pd784217, 784218, 78f4218) 1.8.1 features ? internal rom correction ? inherits the peripheral functions of the m pd78078 subseries ? minimum instruction execution time ? 160 ns (main system clock: f xx = 12.5-mhz operation) ? 61 m s (subsystem clock: f xt = 32.768-khz operation) ? instruction set suited for control applications ? interrupt controller (4-level priority) ? vectored interrupt servicing/macro service/context switching ? standby function ? halt/stop/idle mode ? in the low power consumption mode: halt/idle mode (subsystem clock operation) ? on-chip memory: mask rom 256 kbytes ( m pd784218) 192 kbytes ( m pd784217) flash memory 256 kbytes ( m pd78f4218) ram 12,800 bytes ? i/o pins: 86 ? software programmable pull-up resistors: 70 inputs ? led direct drive possible: 22 outputs ? transistor direct drive possible: 6 outputs ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 6 units ? watch timer: 1 channel ? watchdog timer: 1 channel ? serial interfaces ? uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o): 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently controlled.) ? clock frequency dividing function ? clock output function: selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt ? buzzer output function: selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 ? external access status function ? power supply voltage: v dd = 1.8 to 5.5 v
55 chapter 1 features of 78k/iv series products 1.8.2 applications cellular phones, phs, cordless phones, cd-rom, audiovisual equipment, etc. 1.8.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784217gc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) mask rom m pd784217gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784218gc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) mask rom m pd784218gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4218gc-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) flash memory m pd78f4218gf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. (2) quality grade part number package quality grade m pd784217gc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) standard m pd784217gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784218gc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) standard m pd784218gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4218gc-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) standard m pd78f4218gf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784218 subseries is under development.
56 chapter 1 features of 78k/iv series products 1.8.4 outline of functions (1/2) product name m pd784217 m pd784218 m pd78f4218 item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time ? 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: at 12.5-mhz operation) ? 61 m s (subsystem clock: at 32.768-khz operation) internal memory rom 192 kbytes 256 kbytes 256 kbytes capacity (mask rom) (mask rom) (flash memory) ram 12,800 bytes memory space 1 mbyte in total of program and data i/o ports total 86 cmos inputs 8 cmos i/o 72 n-ch open-drain i/o 6 pins with added pins with pull-up 70 functions note resistors led direct drive outputs 22 medium voltage pins 6 real-time output ports 4 bits 2, or 8 bits 1 timer/counters timer/counter: timer register 1 pulse output possible (16 bits) capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output timer/counter 1: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 2: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 5: timer register 1 pulse output possible ` (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 6: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 7: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 8: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output note the pins with additional functions are included in the i/o pins.
57 chapter 1 features of 78k/iv series products (2/2) product name m pd784217 m pd784218 m pd78f4218 item serial interfaces ? uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel standby function ? halt/stop/idle mode ? in the low power consumption mode (cpu operation by subsystem clock): halt/idle mode interrupts hardware sources 29 (internal: 20, external: 9) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 8 ? 4-level programmable priority ? three processing formats: vectored interrupt, macro service, context switching power supply voltage v dd = 1.8 to 5.5 v package ? 100-pin plastic qfp (fine pitch) (14 14 mm) ? 100-pin plastic qfp (14 20 mm)
58 chapter 1 features of 78k/iv series products 1.8.5 block diagram intp2/nmi intp0,intp1, intp3 to intp6 programmable interrupt controller real-time output port timer/counter 7 (8 bits) timer/counter 8 (8 bits) timer/counter6 (8 bits) timer/counter5 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 ti5/to5 ti6/to6 ti7/to7 ti8/to8 rtp0 to rtp7 clock output control a/d converter av ss av dd pcl buzzer output buz av ref0 ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface si0 so0 sck0 bus i/f rd astb wr wait a0 to a7 ad0 to ad7 a8 to a15 a16 to a19 port0 p00 to p06 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port8 p80 to p87 port9 p90 to p95 port10 p100 to p103 port12 p120 to p127 port13 p130,p131 system control reset xt2 x1 xt1 x2 v ss v dd test/v pp note note the v pp pin applies to the m pd78f4218 only. remark internal rom capacity varies depending on the products.
59 chapter 1 features of 78k/iv series products 1.9 product outline of m pd784218y subseries ( m pd784217y, 784218y, 78f4218y) 1.9.1 features ? adds the i 2 c bus interface to the m pd784218 subseries. ? internal rom correction ? inherits the peripheral functions of the m pd78078y subseries ? minimum instruction execution time ? 160 ns (main system clock: f xx = 12.5-mhz operation) ? 61 m s (subsystem clock: f xt = 32.768-khz operation) ? instruction set suited for control applications ? interrupt controller (4-level priority) ? vectored interrupt servicing/macro service/context switching ? standby function ? halt/stop/idle mode ? in the low power consumption mode: halt/idle mode (subsystem clock operation) ? on-chip memory: mask rom 256 kbytes ( m pd784218y) 192 kbytes ( m pd784217y) flash memory 256 kbytes ( m pd78f4218y) ram 12,800 bytes ? i/o pins: 86 ? software programmable pull-up resistors: 70 inputs ? led direct drive possible: 22 outputs ? transistor direct drive possible: 6 outputs ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 6 units ? watch timer: 1 channel ? watchdog timer: 1 channel ? serial interfaces ? uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o, multimaster supported i 2 c bus): 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently controlled.) ? clock frequency dividing function ? clock output function: selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt ? buzzer output function: selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 ? external access status function ? power supply voltage: v dd = 1.8 to 5.5 v
60 chapter 1 features of 78k/iv series products 1.9.2 applications cellular phones, phs, cordless phones, cd-rom, audiovisual equipment, etc. 1.9.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784217ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) mask rom m pd784217ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784218ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) mask rom m pd784218ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4218ygc-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) flash memory m pd78f4218ygf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. (2) quality grade part number package quality grade m pd784217ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) standard m pd784217ygf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784218ygc- -7ea 100-pin plastic qfp (fine pitch) (14 14 mm) standard m pd784218ygf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4218ygc-7ea 100-pin plastic qfp (fine pitch) (14 14 mm) standard m pd78f4218ygf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784218y subseries is under development.
61 chapter 1 features of 78k/iv series products 1.9.4 outline of functions (1/2) product name m pd784217y m pd784218y m pd78f4218y item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time ? 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: at 12.5-mhz operation) ? 61 m s (subsystem clock: at 32.768-khz operation) internal memory rom 192 kbytes 250 kbytes 256 kbytes capacity (mask rom) (mask rom) (flash memory) ram 12,800 bytes memory space 1 mbyte in total of program and data i/o ports total 86 cmos inputs 8 cmos i/o 72 n-ch open-drain i/o 6 pins with added pins with pull-up 70 functions note resistors led direct drive outputs 22 medium voltage pins 6 real-time output ports 4 bits 2, or 8 bits 1 timer/counters timer/counter: timer register 1 pulse output possible (16 bits) capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output timer/counter 1: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 2: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 5: timer register 1 pulse output possible ` (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 6: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 7: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 8: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output note the pins with additional functions are included in the i/o pins.
62 chapter 1 features of 78k/iv series products (2/2) product name m pd784217y m pd784218y m pd78f4218y item serial interfaces ? uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o, multimaster supported i 2 c bus): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel standby function ? halt/stop/idle mode ? in the low power consumption mode (cpu operation by subsystem clock): halt/idle mode interrupts hardware sources 29 (internal: 20, external: 9) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 8 ? 4-level programmable priority ? three processing formats: vectored interrupt, macro service, context switching power supply voltage v dd = 1.8 to 5.5 v package ? 100-pin plastic qfp (fine pitch) (14 14 mm) ? 100-pin plastic qfp (14 20 mm)
63 chapter 1 features of 78k/iv series products 1.9.5 block diagram intp2/nmi intp0,intp1, intp3 to intp6 programmable interrupt controller real-time output port timer/counter 7 (8 bits) timer/counter 8 (8 bits) timer/counter6 (8 bits) timer/counter5 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 ti5/to5 ti6/to6 ti7/to7 ti8/to8 rtp0 to rtp7 clock output control a/d converter av ss av dd pcl buzzer output buz av ref0 ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface si0/sda0 so0 sck0/scl0 bus i/f rd astb wr wait a0 to a7 ad0 to ad7 a8 to a15 a16 to a19 port0 p00 to p06 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port8 p80 to p87 port9 p90 to p95 port10 p100 to p103 port12 p120 to p127 port13 p130,p131 system control reset xt2 x1 xt1 x2 v ss v dd test/v pp note note the v pp pin applies to the m pd78f4218y only. remark internal rom capacity varies depending on the products.
64 chapter 1 features of 78k/iv series products 1.10 product outline of m pd784225 subseries ( m pd784224, 784225, 78f4225) 1.10.1 features ? inherits the peripheral functions of the m pd780058 subseries ? minimum instruction execution time ? 160 ns (main system clock: f xx = 12.5-mhz operation) ? 61 m s (subsystem clock: f xt = 32.768-khz operation) ? instruction set suited for control applications ? interrupt controller (4-level priority) ? vectored interrupt servicing/macro service/context switching ? standby function ? halt/stop/idle mode ? in the low power consumption mode: halt/idle mode (subsystem clock operation) ? on-chip memory: mask rom 128 kbytes ( m pd784225) 96 kbytes ( m pd784224) flash memory 128 kbytes ( m pd78f4225) ram 4,352 bytes ( m pd784225, 78f4225) 3,584 bytes ( m pd784224) ? i/o pins: 67 ? software programmable pull-up resistors: 50 inputs ? led direct drive possible: 16 outputs ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 4 units ? watch timer: 1 channel ? watchdog timer: 1 channel ? serial interfaces ? uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o): 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? real-time output port (by combining with the timer/counter, two systems of stepping motors can be independently controlled.) ? clock frequency division function ? clock output function: selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt ? buzzer output function: selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 ? power supply voltage: v dd = 1.8 to 5.5 v
65 chapter 1 features of 78k/iv series products 1.10.2 applications car audio, portable audio, air conditioner, telephone, etc. 1.10.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784224gc- -8bt 80-pin plastic qfp (14 14 mm) mask rom m pd784224gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784225gc- -8bt 80-pin plastic qfp (14 14 mm) mask rom m pd784225gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd78f4225gc-8bt 80-pin plastic qfp (14 14 mm) flash memory m pd78f4225gk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) flash memory remark indicates rom code suffix. (2) quality grade part number package quality grade m pd784224gc- -8bt 80-pin plastic qfp (14 14 mm) standard m pd784224gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784225gc- -8bt 80-pin plastic qfp (14 14 mm) standard m pd784225gk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78f4225gc-8bt 80-pin plastic qfp (14 14 mm) standard m pd78f4225gk-be9 80-pin plastic tqfp (fine pitch) (12 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784225 subseries is under development.
66 chapter 1 features of 78k/iv series products 1.10.4 outline of functions (1/2) product name m pd784224 m pd784225 m pd78f4225 item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time ? 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: at 12.5-mhz operation) ? 61 m s (subsystem clock: at 32.768-khz operation) internal memory rom 96 kbytes 128 kbytes 128 kbytes capacity (mask rom) (mask rom) (flash memory) ram 3,584 bytes 4,352 bytes memory space 1 mbyte in total of program and data i/o ports total 67 cmos inputs 8 cmos i/o 59 pins with added pins with pull-up 57 functions note resistors led direct drive outputs 16 real-time output ports 4 bits 2, or 8 bits 1 timer/counters timer/counter: timer register 1 pulse output possible (16 bits) capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output timer/counter 1: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 2: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 5: timer register 1 ` (8 bits) compare register 1 timer/counter 6: timer register 1 (8 bits) compare register 1 serial interfaces ? uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel note the pins with additional functions are included in the i/o pins.
67 chapter 1 features of 78k/iv series products (2/2) product name m pd784224 m pd784225 m pd78f4225 item standby function ? halt/stop/idle mode ? in the low power consumption mode (cpu operation by subsystem clock): halt/idle mode interrupts hardware sources 25 (internal: 18, external: 7) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 17, external: 6 ? 4-level programmable priority ? three processing formats: vectored interrupt, macro service, context switching power supply voltage v dd = 1.8 to 5.5 v package ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin plastic qfp (14 14 mm)
68 chapter 1 features of 78k/iv series products 1.10.5 block diagram intp2/nmi intp0,intp1, intp3 to intp5 programmable interrupt controller real-time output port timer/counter 5 (8 bits) timer/counter 6 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 rtp0 to rtp7 clock output control a/d converter av ss av dd pcl buzzer output buz ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface si0 so0 sck0 bus i/f rd astb exa wr wait a0 to a7 a8 to a15 a16 to a19 port0 p00 to p05 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port12 p120 to p127 port13 p130,p131 system control reset xt2 x1 xt1 x2 v ss0 , v ss1 v dd0 , v dd1 test/v pp note note the v pp pin applies to the m pd78f4225 only. remark internal rom and ram capacities vary depending on the products.
69 chapter 1 features of 78k/iv series products 1.11 product outline of m pd784225y subseries ( m PD784224Y, 784225y, 78f4225y) 1.11.1 features ? adds the i 2 c bus interface to the m pd784225 subseries. ? inherits the peripheral functions of the m pd780058y subseries ? minimum instruction execution time ? 160 ns (main system clock: f xx = 12.5-mhz operation) ? 61 m s (subsystem clock: f xt = 32.768-khz operation) ? instruction set suited for control applications ? interrupt controller (4-level priority) ? vectored interrupt servicing/macro service/context switching ? standby function ? halt/stop/idle mode ? in the low power consumption mode: halt/idle mode (subsystem clock operation) ? on-chip memory: mask rom 128 kbytes ( m pd784225y) 96 kbytes ( m PD784224Y) flash memory 128 kbytes ( m pd78f4225y) ram 4,352 bytes ( m pd784225y, 78f4225y) 3,584 bytes ( m PD784224Y) ? i/o pins: 67 ? software programmable pull-up resistors: 50 inputs ? led direct drive possible: 16 outputs ? timer/counter: 16-bit timer/counter 1 unit 8-bit timer/counter 4 units ? watch timer: 1 channel ? watchdog timer: 1 channel ? serial interfaces ? uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o, multimaster supported i 2 c bus): 1 channel ? a/d converter: 8-bit resolution 8 channels ? d/a converter: 8-bit resolution 2 channels ? real-time output port (by combining with the timer/counter, two stepping motors can be independently controlled.) ? clock frequency dividing function ? clock output function: selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt ? buzzer output function: selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 ? external access status function ? power supply voltage: v dd = 1.8 to 5.5 v
70 chapter 1 features of 78k/iv series products 1.11.2 applications car audios, portable audios, air conditioners, telephones, etc. 1.11.3 ordering information and quality grade (1) ordering information part number package internal rom m PD784224Ygc- -8bt 80-pin plastic qfp (14 14 mm) mask rom m PD784224Ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd784225ygc- -8bt 80-pin plastic qfp (14 14 mm) mask rom m pd784225ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) mask rom m pd78f4225ygc-8bt 80-pin plastic qfp (14 14 mm) flash memory m pd78f4225ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) flash memory remark indicates rom code suffix. (2) quality grade part number package quality grade m PD784224Ygc- -8bt 80-pin plastic qfp (14 14 mm) standard m PD784224Ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd784225ygc- -8bt 80-pin plastic qfp (14 14 mm) standard m pd784225ygk- -be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard m pd78f4225ygc-8bt 80-pin plastic qfp (14 14 mm) standard m pd78f4225ygk-be9 80-pin plastic tqfp (fine pitch) (12 12 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784225y subseries is under development.
71 chapter 1 features of 78k/iv series products 1.11.4 outline of functions (1/2) product name m PD784224Y m pd784225y m pd78f4225y item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time ? 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: at 12.5-mhz operation) ? 61 m s (subsystem clock: at 32.768-khz operation) internal memory rom 96 kbytes 128 kbytes 128 kbytes capacity (mask rom) (mask rom) (flash memory) ram 3,584 bytes 4,352 bytes memory space 1 mbyte in total of program and data ? i/o ports total 67 ? cmos inputs 8 ? cmos i/o 59 pins with added ? pins with pull-up 57 functions note ? led direct drive outputs 16 ? real-time output ports 4 bits 2, or 8 bits 1 timer/counters timer/counter: timer register 1 pulse output possible (16 bits) capture/compare register 2 ? pwm/ppg output ? square wave output ? one-shot pulse output timer/counter 1: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 2: timer register 1 pulse output possible (8 bits) compare register 1 ? pwm output ? square wave output timer/counter 5: timer register 1 ` (8 bits) compare register 1 timer/counter 6: timer register 1 (8 bits) compare register 1 serial interfaces ? uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) ? csi (3-wire serial i/o, multimaster supported i 2 c bus): 1 channel a/d converter 8-bit resolution 8 channels d/a converter 8-bit resolution 2 channels clock output selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 , f xx /2 6 , f xx /2 7 , f xt buzzer output selectable from f xx /2 10 , f xx /2 11 , f xx /2 12 , f xx /2 13 watch timer 1 channel watchdog timer 1 channel note the pins with additional functions are included in the i/o pins.
72 chapter 1 features of 78k/iv series products (2/2) product name m PD784224Y m pd784225y m pd78f4225y item standby function ? halt/stop/idle mode ? in the low power consumption mode (cpu operation by subsystem clock): halt/idle mode interrupts hardware sources 25 (internal: 18, external: 7) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 17, external: 6 ? 4-level programmable priority ? three processing formats: vectored interrupt, macro service, context switching power supply voltage v dd = 1.8 to 5.5 v package ? 80-pin plastic tqfp (fine pitch) (12 12 mm) ? 80-pin plastic qfp (14 14 mm)
73 chapter 1 features of 78k/iv series products 1.11.5 block diagram intp2/nmi intp0,intp1, intp3 to intp5 programmable interrupt controller real-time output port timer/counter 5 (8 bits) timer/counter 6 (8 bits) timer/counter2 (8 bits) timer/counter1 (8 bits) timer/counter (16 bits) watch timer watchdog timer ti00 ti01 to0 ti1 to1 ti2 to2 rtp0 to rtp7 clock output control a/d converter av ss av dd pcl buzzer output buz ani0 to ani7 d/a converter ano0 av ss av ref1 ano1 78k/iv cpu core rom ram baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 rxd1/si1 txd1/so1 asck1/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface si0/sda0 so0 sck0/scl0 bus i/f rd astb exa wr wait a0 to a7 a8 to a15 a16 to a19 port0 p00 to p05 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p72 port12 p120 to p127 port13 p130,p131 system control reset xt2 x1 xt1 x2 v ss0 , v ss1 v dd0 , v dd1 test/v pp note note the v pp pin applies to the m pd78f4225y only. remark internal rom and ram capacities vary depending on the products.
74 chapter 1 features of 78k/iv series products 1.12 product outline of m pd784908 subseries ( m pd784907, 784908, 78p4908) 1.12.1 features ? minimum instruction execution time: 160 ns (at 12.58-mhz operation) ? on-chip memory ? mask rom : 96 kbytes ( m pd784907) 128 kbytes ( m pd784908) prom : 128 kbytes ( m pd78p4908) ? ram : 3,584 bytes ( m pd784907) 4,352 bytes ( m pd784908, 78p4908) ? i/o port: 80 ? timer/counter: 16-bit timer/counter 3 units 16-bit timer 1 unit ? watch timer: 1 channel ? watchdog timer: 1 channel ? serial interfaces: 4 channels ? uart/ioe (3-wire serial i/o): 2 channels ? csi (3-wire serial i/o): 2 channels ? standby function ? halt/stop/idle mode ? clock frequency dividing function ? clock output function: selectable from f clk , f clk /2, f clk /4, f clk /8, f clk /16 ? a/d converter: 8-bit resolution 8 channels ? internal iebus controller ? low power consumption ? power supply voltage: v dd = 3.5 to 5.5 v (mask rom version) v dd = 4.0 to 5.5 v (prom version)
75 chapter 1 features of 78k/iv series products 1.12.2 applications car audios, etc. 1.12.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784907gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784908gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78p4908gf-3ba 100-pin plastic qfp (14 20 mm) one-time prom remark indicates rom code suffix. (2) quality grade part number package quality grade m pd784907gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784908gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78p4908gf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784908 subseries is under development.
76 chapter 1 features of 78k/iv series products 1.12.4 outline of functions (1/2) product name m pd784907 m pd784908 m pd78p4908 item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time 160 ns/320 ns/636 ns/1.27 m s (at 12.58-khz operation) internal memory rom 92 kbytes 128 kbytes 128 kbytes capacity (mask rom) (mask rom) (prom) ram 3,584 bytes 4,352 bytes memory space 1 mbyte in total of program and data i/o ports total 80 inputs 8 i/o 72 pins with added led direct drive 24 functions note outputs transistor direct drive 8 n-ch open-drain 4 real-time output ports 4 bits 2, or 8 bits 1 iebus controller internal (simplify) timer/counters timer/counter 0: timer register 1 pulse output capability (16 bits) capture register 1 ? toggle output compare register 2 ? pwm/ppg output ? one-shot pulse output timer/counter 1: timer register 1 real-time output port (16 bits) capture register 1 capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability capture register 1 ? toggle output capture/compare register 1 ? pwm/ppg output compare register 1 timer 3: timer register 1 compare register 1 watch timer interrupt occurs at an interval of 0.5 sec. (has an internal clock oscillator.) the input clock can be selected from among the main clock (12.58 mhz) or clock (32.7 khz). clock output selectable from f clk , f clk /2, f clk /4, f clk /8, f clk /16, (also usable as output port) pwm output 12-bit resolution 2 channels serial interfaces uart/ioe (3-wire serial i/o): 2 channels (on-chip baud rate generator) csi (3-wire serial i/o): 2 channels a/d converter 8-bit resolution 8 channels watchdog timer 1 channel standby function halt/stop/idle mode note the pins with additional functions are included in the i/o pins.
77 chapter 1 features of 78k/iv series products (2/2) product name m pd784907 m pd784908 m pd78f4908 item interrupts hardware sources 27 (internal: 20, external: 7 (sampling clock variable input: 1)) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 6 4-level programmable priority three processing formats: vectored interrupt, macro service, context switching power supply voltage v dd = 3.5 to 5.5 v v dd = 4.0 to 5.5 v package 100-pin plastic qfp (14 20 mm)
78 chapter 1 features of 78k/iv series products 1.12.5 block diagram nmi intp0 to intp5 programmable interrupt controller real-time output port timer 3 (16 bits) timer/counter2 (8 bits) timer/counter1 (16 bits) timer/counter0 (16 bits) watch timer watchdog timer pwm intp3 to0 to1 intp0 intp1 intp5 intp2/ci to2 to3 p00 to p03 p04 to p07 a/d converter av ref1 av ss av dd ani0 to ani7 iebus controller tx pwm0 pwm1 rx 78k/iv cpu core rom ram baud-rate generator uart/ioe2 baud-rate generator uart/ioe1 rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 clocked serial interface sck0 so0 si0 clocked serial interface3 sck3 so3 si3 bus i/f clock output rd refrq/hldak astb/clkout wr wait/hldrq ad0 to ad7 a8 to a15 a16 to a19 port0 p00 to p07 port1 p10 to p17 port2 p20 to p27 port3 p30 to p37 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port7 p70 to p77 port9 p90 to p97 port10 p100 to p107 system control (regulator) reset regoff x1 regc x2 xt1 xt2 v ss v dd test remark internal rom and ram capacities vary depending on the products.
79 chapter 1 features of 78k/iv series products 1.13 product outline of m pd784915 subseries ( m pd784915, 784915a, 784916a, 784915b, 784916b, 78p4916) 1.13.1 features ? 78k/iv series (16-bit cpu core employed): minimum instruction execution time: 250 ns (at 8-mhz internal clock) ? internal timer unit for vcr servo control (super timer unit) ? internal analog circuit for vhs type vcr ? ctl amplifier ? recctl driver (supports rewriting) ? dpfg separation circuit (ternary separation circuit) ? dfg amplifier, dpg comparator, cfg amplifier ? reel fg comparator (2 channels), csync comparator ? i/o port: 54 ? serial interface: 2 channels (3-wire serial i/o) ? a/d converter: 12 channels (conversion time: 10 m s) ? pwm output: 16-bit resolution 3 channels, 8-bit resolution 3 channels ? interrupt function ? vectored interrupt function ? macro service function ? context switching function ? low-frequency oscillation mode supported: main system clock frequency = internal clock frequency ? low-power consumption mode: cpu can operate on subsystem clock. ? hardware watch function: watch operation on low voltage (v dd = 2.5 v (min.)) and with low current consumption ? package for high-density mounting: 100-pin plastic qfp (0.65-mm pitch, 14 20 mm) 1.13.2 applications for controlling system/servo/timer of vcr (stationary type and camcorder type)
80 chapter 1 features of 78k/iv series products 1.13.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784915gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784915agf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784916agf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784915bgf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784916bgf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78p4916gf-3ba 100-pin plastic qfp (14 20 mm) one-time prom remark indicates rom code suffix. (2) quality grades part number package quality grade m pd784915gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784915agf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784916agf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784915bgf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784916bgf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78p4916gf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix.
81 chapter 1 features of 78k/iv series products 1.13.4 outline of functions product name m pd784915, m pd784915b m pd784916a m pd784916b m pd78p4916 item 784915a number of instructions 113 minimum instruction execution time 250 ns (8-mhz internal clock operation) internal memory capacity 48 kbytes 62 kbytes 62 kbytes (mask rom) (mask rom) (one-time prom) ram 1,280 bytes 2,048 bytes interrupt 4 levels (programmable), vector interrupt, macro service, context switching external source 9 (including nmi) internal source 19 number of interrupts that can use macro 25 service types of macro services 4 types, 10 macro services i/o port input: 8, i/o: 46 time base counter ? 22-bit frc ? resolution: 125 ns, maximum count time: 524 ms capture register input signal number of bits measurement cycle operating edge cfg 22 125 ns to 524 ms ? dfg 22 125 ns to 524 ms hsw 16 1 m s to 65.5 ms ? v sync 22 125 ns to 524 ms ctl 16 1 m s to 65.5 ms ? t reel 22 125 ns to 524 ms ? s reel 22 125 ns to 524 ms ? general-purpose timer 16-bit timer 3 pbctl duty identification ? duty of playback control signal ? viss detection, wide aspect detection linear time counter 5-bit udc for counting ctl signal real-time output port 11 serial interface clocked (3-wire): 2 channels a/d converter 8-bit resolution 12 channels, conversion time: 10 m s pwm output ? 16-bit resolution 3 channels, 8-bit resolution 3 channels ? carrier frequency: 62.5 khz watch function 0.5-sec measurement, low-voltage operation standby function halt mode/stop mode analog circuit ? ctl amplifier ? recctl driver (supports rewriting) ? dpfg separation circuit (ternary separation circuit) ? dfg amplifier, dpg comparator, cfg amplifier ? reel fg comparator ? csync comparator power supply voltage v dd = 2.7 to 5.5 v package 100-pin plastic qfp (14 20 mm) rom
82 chapter 1 features of 78k/iv series products 1.13.5 block diagram remarks 1. internal rom and ram capacities vary depending on the products. 2. v pp applies to the m pd78p4916 only. 3. the pins in parentheses are used in the prom programming mode. nmi intp0 to intp3 pwm0 to pwm5 pto00 to pto02 pto10, pto11 vrefc reeel0in reeel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl+ recctl ctldly av dd1 , av dd2 av ss1 , av ss2 av ref ani0 to ani11 si1 so1 sck1 si2/busy so2 sck2 strb interrupt control super timer unit analog unit & a/d converter serial interface 1 serial interface 2 ram rom 78k/iv 16-bit cpu core system control clock output buzzer output key input real- time output port port0 port4 port5 port6 port7 port8 port9 v dd v ss x1 x2 xt1 xt2 reset (d0 to d7) (a0 to a16) (ce) (oe) (pgm) (v pp ) clo buz key0 to key4 p00 to p07 p80, p82, p83 p00 to p07 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p80, p82 to p87 p90 to p96
83 chapter 1 features of 78k/iv series products 1.14 product outline of m pd784928 subseries ( m pd784927, 78f4928) 1.14.1 features ? 16-bit cpu core: minimum instruction execution time: 250 ns (with 8-mhz internal clock) ? internal timer unit (super timer unit) for vcr servo control ? i/o ports: 74 ? internal analog circuits for vhs type vcr ? ctl amplifier ? recctl driver (supporting rewrite) ? cfg amplifier ? dfg amplifier ? dpg amplifier ? dpfg separation circuit (ternary separation circuit) ? reel fg comparator (2 channels) ? csync comparator ? serial interface: 2 channels ? 3-wire serial i/o: 2 channels ? a/d converter: 12 channels (conversion time: 10 m s) ? pwm output: 16-bit resolution 3 channels, 8-bit resolution 3 channels ? interrupt function ? vector interrupt function ? macro service function ? context switching function ? low frequency oscillation mode: main system clock frequency = internal clock frequency ? low power consumption mode: cpu can operate on subsystem clock. ? power supply voltage: v dd = 2.7 to 5.5 v ? hardware watch function: low-voltage (v dd = 2.7 v min.), low-current consumption operation 1.14.2 applications for stationary type and camcorder type vcrs.
84 chapter 1 features of 78k/iv series products 1.14.3 ordering information (1) ordering information part number package internal rom m pd784927gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4928gf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. (2) quality grade part number package quality grade m pd784927gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4928gf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix.
85 chapter 1 features of 78k/iv series products 1.14.4 outline of functions product name m pd784927 m pd78f4928 item number of instructions 113 minimum instruction execution time 250 ns (internal clock: 8-mhz operation) internal memory capacity rom 96 kbytes (mask rom) 128 kbytes (flash memory) ram 2,048 bytes 3,584 bytes interrupt sources external 9 (including nmi) internal 22 (including software interrupt) ? 4 levels programmable priority ? 3 types of processing methods vectored interrupt, macro service, context switching i/o ports input 20 i/o 54 (including led direct drive ports: 8) time base counter ? 22-bit frc ? resolution: 125 ns, maximum count time: 524 ms capture registers input signal number of bits measuring cycle operating edge cfg 22 125 ns to 524 ms ? dfg 22 125 ns to 524 ms hsw 16 1 m s to 65.5 ms ? v sync 22 125 ns to 524 ms ctl 16 1 m s to 65.5 ms ? t reel 22 125 ns to 524 ms ? s reel 22 125 ns to 524 ms ? general-purpose timer 16-bit timer 3 pbctl duty identification ? identifies duty of recording control signal ? viss detection, wide aspect detection linear time counter 5-bit udc counts ctl signal real-time output port 11 serial interface 3-wire serial i/o: 2 channels (including busy/strb control possible: 1 channel) buzzer output function 1.95 khz, 3.91 khz, 7.81 khz, 15.6 khz (internal: 8-mhz operation) 2.048 khz, 4.096 khz, 32.768 khz (subsystem clock: 32.768-khz operation) a/d converter 8-bit resolution 12 channels, conversion time: 10 m s pwm output ? 16-bit resolution 3 channels, 8-bit resolution 3 channels ? carrier frequency: 62.5 khz watch function 0.5-second measurement, low-voltage operation (v dd = 2.7 v) possible standby function halt mode/stop mode/low power consumption mode/low power consumption halt mode analog circuits ? ctl amplifier ? dpg amplifier ? recctl driver (rewriting supported) ? dpfg separation circuit ? cfg amplifier (ternary separation circuit) ? dfg amplifier ? reel fg comparator ? csync comparator power supply voltage v dd = +2.7 to 5.5 v package 100-pin plastic qfp (14 20 mm)
86 chapter 1 features of 78k/iv series products 1.14.5 block diagram note the v pp pin applies to the m pd78f4928 only. remark internal rom and ram capacities vary depending on the products. nmi intp0 to intp3 pwm0 to pwm5 pto00 to pto02 pto10, pto11 vrefc reel0in reel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl+ recctl ctldly dfgmon dpgmon cfgmon ctlmon av dd1 , av dd2 av ss1 , av ss2 av ref ani0 to ani11 si1 so1 sck1 si2/busy so2 sck2 strb interrupt control super timer unit analog unit & a/d converter serial interface 1 serial interface 2 ram rom 78k/iv 16-bit cpu core (ram: 512 bytes) clock output buzzer output key input real- time output port system control v dd v ss x1 x2 xt1 xt2 reset v pp note clo buz key0 to key4 p00 to p07 p80, p82, p83 port3 p30 to p37 port2 p20 to p23 port0 p00 to p07 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port8 p80, p82 to p87 port10 p100 to p103 port11 p110 to p113 port9 p90 to p96 port7 p70 to p77
87 chapter 1 features of 78k/iv series products 1.15 product outline of m pd784928y subseries ( m pd784927y, 78f4928y) 1.15.1 features ? add the i 2 c bus interface to the m pd784928 subseries. ? 16-bit cpu core: minimum instruction execution time: 250 ns (at 8-mhz internal clock) ? internal timer unit (super timer unit) for vcr servo control ? i/o ports: 74 ? internal analog circuits for vhs type vcr ? ctl amplifier ? recctl driver (supporting rewrite) ? cfg amplifier ? dfg amplifier ? dpg amplifier ? dpfg separation circuit (ternary separation circuit) ? reel fg comparator (2 channels) ? csync comparator ? serial interface: 2 channels ? 3-wire serial i/o: 2 channels ?i 2 c bus interface: 1 channel ? a/d converter: 12 channels (conversion time: 10 m s) ? pwm output: 16-bit resolution 3 channels, 8-bit resolution 3 channels ? interrupt function ? vector interrupt function ? macro service function ? context switching function ? low frequency oscillation mode: main system clock frequency = internal clock frequency ? low power consumption mode: cpu can operate on subsystem clock. ? power supply voltage: v dd = 2.7 to 5.5 v ? hardware watch function: low-voltage (v dd = 2.7 v min.), low-current consumption operation 1.15.2 applications for stationary type and camcorder type vcrs.
88 chapter 1 features of 78k/iv series products 1.15.3 ordering information (1) ordering information part number package internal rom m pd784927ygf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd78f4928ygf-3ba 100-pin plastic qfp (14 20 mm) flash memory remark indicates rom code suffix. (2) quality grade part number package quality grade m pd784927ygf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4928ygf-3ba 100-pin plastic qfp (14 20 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix.
89 chapter 1 features of 78k/iv series products 1.15.4 outline of functions product name m pd784927y m pd78f4928y item number of instructions 113 minimum instruction execution time 250 ns (internal clock: 8-mhz operation) internal memory capacity rom 96 kbytes (mask rom) 128 kbytes (flash memory) ram 2,048 bytes 3,584 bytes interrupt sources external 9 (including nmi) internal 23 (including software interrupt) ? 4 levels programmable priority ? 3 types of processing methods vectored interrupt, macro service, context switching i/o ports input 20 i/o 54 (including led direct drive ports: 8) time base counter ? 22-bit frc ? resolution: 125 ns, maximum count time: 524 ms capture registers input signal number of bits measuring cycle operating edge cfg 22 125 ns to 524 ms ? dfg 22 125 ns to 524 ms hsw 16 1 m s to 65.5 ms ? v sync 22 125 ns to 524 ms ctl 16 1 m s to 65.5 ms ? t reel 22 125 ns to 524 ms ? s reel 22 125 ns to 524 ms ? general-purpose timer 16-bit timer 3 pbctl duty identification ? identifies duty of recording control signal ? viss detection, wide aspect detection linear time counter 5-bit udc counts ctl signal real-time output port 11 serial interface ? 3-wire serial i/o: 2 channels (including busy/strb control possible: 1 channel) ?i 2 c bus interface (multimaster supported): 1 channel buzzer output function 1.95 khz, 3.91 khz, 7.81 khz, 15.6 khz (internal: 8-mhz operation) 2.048 khz, 4.096 khz, 32.768 khz (subsystem clock: 32.768-khz operation) a/d converter 8-bit resolution 12 channels, conversion time: 10 m s pwm output ? 16-bit resolution 3 channels, 8-bit resolution 3 channels ? carrier frequency: 62.5 khz watch function 0.5-second measurement, low-voltage operation (v dd = 2.7 v) possible standby function halt mode/stop mode/low power consumption mode/low power consumption halt mode analog circuits ? ctl amplifier ? dpg amplifier ? recctl driver (rewriting supported) ? dpfg separation circuit ? cfg amplifier (ternary separation circuit) ? dfg amplifier ? reel fg comparator ? csync comparator power supply voltage v dd = +2.7 to 5.5 v package 100-pin plastic qfp (14 20 mm)
90 chapter 1 features of 78k/iv series products 1.15.5 block diagram notes 1. the v pp pin applies to the m pd78f4928y only. 2. i 2 c bus interface supported. remark internal rom and ram capacities vary depending on the products. nmi intp0 to intp3 pwm0 to pwm5 pto00 to pto02 pto10, pto11 vrefc reel0in reel1in csyncin dfgin dpgin cfgin cfgampo cfgcpin ctlout1 ctlout2 ctlin recctl+ recctl ctldly dfgmon dpgmon cfgmon ctlmon av dd1 , av dd2 av ss1 , av ss2 av ref ani0 to ani11 si1 so1 sck1 si2/busy so2 sck2 strb interrupt control super timer unit analog unit & a/d converter serial interface 1 serial interface 2 sda scl serial note 2 interface 3 ram rom 78k/iv 16-bit cpu core (ram: 512 bytes) clock output buzzer output key input real- time output port system control v dd v ss x1 x2 xt1 xt2 reset v pp note 1 clo buz key0 to key4 p00 to p07 p80, p82, p83 port3 p30 to p37 port2 p20 to p23 port0 p00 to p07 port4 p40 to p47 port5 p50 to p57 port6 p60 to p67 port8 p80, p82 to p87 port10 p100 to p103 port11 p110 to p113 port9 p90 to p96 port7 p70 to p77
91 chapter 1 features of 78k/iv series products 1.16 product outline of m pd784937 subseries ( m pd784935, 784936, 78f4937, 78f4937) 1.16.1 features ? inherits the peripheral functions of the m pd784908 subseries ? minimum instruction execution time: 160 ns (at f xx = 12.5-mhz operation) ? on-chip memory ? mask rom : 96 kbytes ( m pd784935) 128 kbytes ( m pd784936) 192 kbytes ( m pd784937) ? flash memory : 192 kbytes ( m pd78f4937) ? ram : 5,120 bytes ( m pd784935) : 6,656 bytes ( m pd784936) : 8,192 bytes ( m pd784937, 78f4937) ? i/o port: 80 ? timer/counter: 16-bit timer/counter 1 unit 16-bit timer/counter 2 units 16-bit timer 1 unit ? serial interface: 4 channels ? uart/ioe (3-wire serial i/o): 2 channels (on-chip baud-rate generator) ? csi (3-wire serial i/o): 2 channels ? pwm output: 2 outputs ? standby function halt/stop/idle mode ? clock frequency dividing function ? clock output function: selectable from f xx , f xx /2, f xx /2 2 , f xx /2 3 , f xx /2 4 , f xx /2 5 ? external expansion function ? internal rom correction function ? a/d converter: 8-bit resolution 8 channels ? internal iebus controller ? watchdog timer: 1 channel ? low power consumption ? power supply voltage: v dd = 2.7 to 5.5 v 1.16.2 applications car audios, etc.
92 chapter 1 features of 78k/iv series products 1.16.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784935gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784935gc- -8eu 100-pin plastic lqfp (14 14 mm) mask rom m pd784936gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784936gc- -8eu 100-pin plastic lqfp (14 14 mm) mask rom m pd784937gf- -3ba 100-pin plastic qfp (14 20 mm) mask rom m pd784937gc- -8eu 100-pin plastic lqfp (14 14 mm) mask rom m pd78f4937gf-3ba 100-pin plastic qfp (14 20 mm) flash memory m pd78f4937gc-8eu 100-pin plastic lqfp (14 14 mm) flash memory remark indicates rom code suffix. (2) quality grades part number package quality grade m pd784935gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784935gc- -8eu 100-pin plastic lqfp (14 14 mm) standard m pd784936gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784936gc- -8eu 100-pin plastic lqfp (14 14 mm) standard m pd784937gf- -3ba 100-pin plastic qfp (14 20 mm) standard m pd784937gc- -8eu 100-pin plastic lqfp (14 14 mm) standard m pd78f4937gf-3ba 100-pin plastic qfp (14 20 mm) standard m pd78f4937gc-8eu 100-pin plastic lqfp (14 14 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784937 subseries is under development.
93 chapter 1 features of 78k/iv series products 1.16.4 outline of functions (1/2) product name m pd784935 m pd784936 m pd784937 m pd78f4937 item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapping) minimum instruction execution time 160 ns/320 ns/636 ns/1.27 m s (at 12.58-khz operation) internal memory rom 92 kbytes 128 kbytes 192 kbytes 192 kbytes capacity (mask rom) (mask rom) (mask rom) (flash memory) ram 5,120 bytes 6,656 bytes 8,192 bytes memory space 1 mbyte in total of program and data i/o ports total 80 inputs 8 i/o 72 pins with added led direct drive 24 functions note outputs transistor direct drive 8 n-ch open-drain 4 real-time output ports 4 bits 2, or 8 bits 1 iebus controller internal (simplify) timer/counters timer/counter 0: timer register 1 pulse output capability (16 bits) capture register 1 ? toggle output compare register 2 ? pwm/ppg output ? one-shot pulse output timer/counter 1: timer register 1 real-time output port (16 bits) capture register 1 capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability (16 bits) capture register 1 ? toggle output capture/compare register 1 ? pwm/ppg output compare register 1 timer 3: timer register 1 pulse output capability (16 bits) compare register 1 ? toggle output ? pwm/ppg output watch timer interrupt occurs at an interval of 0.5 sec. (has an internal clock oscillator.) the input clock can be selected from among the main clock (12.58 mhz) or clock (32.7 khz). pwm output 12-bit resolution 2 channels serial interfaces uart/ioe (3-wire serial i/o) : 2 channels (on-chip baud rate generator) csi (3-wire serial i/o): 2 channels a/d converter 8-bit resolution 8 channels clock output function selectable from f clk , f clk /2, f clk /4, f clk /8, f clk /16 (can be used as 1-bit output port) watchdog timer 1 channel note the pins with additional functions are included in the i/o pins.
94 chapter 1 features of 78k/iv series products (2/2) product name m pd784935 m pd784936 m pd784937 m pd78f4937 item rom correction function internal (can be set for 4 points of correction address) external expansion function available (can be set up to 1 mbyte) standby function halt/stop/idle mode interrupts hardware sources 27 (internal: 20, external: 7 (sampling clock variable input: 1)) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 19, external: 6 4-level programmable priority three processing formats: macro service/vectored interrupt/context switching power supply voltage v dd = 2.7 to 5.5 v package ? 100-pin plastic qfp (14 20 mm) ? 100-pin plastic lqfp (14 14 mm)
95 chapter 1 features of 78k/iv series products 1.16.5 block diagram note in the flash memory programming mode of the m pd78f4937. remark internal rom and ram capacities vary depending on the products. programmable interrupt controller timer/counter0 (16 bits) timer/counter1 (16 bits) timer/counter2 (16 bits) timer3 (16 bits) real-time output port pwm a/d converter 78k/iv cpu core rom ram watchdog timer uart/ioe2 baud-rate generator uart/ioe1 baud-rate generator clocked serial interface clock output bus i/f port0 port1 port2 port3 port4 port5 port6 port7 nmi intp0 to intp5 intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00 to p03 p04 to p07 pwm0 pwm1 iebus controller tx rx ani0 to ani7 av dd av ref1 av ss intp5 rxd/si1 txd/so1 asck/sck1 rxd2/si2 txd2/so2 asck2/sck2 sck0 so0 si0 clocked serial interface3 sck3 so3 si3 astb/clkout ad0 to ad7 a8 to a15 rd wr wait/hldrq refrq/hldak p00 to p07 p10 to p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 port9 port10 p90 to p97 p100 to p107 watch timer xt1 xt2 reset ic/v pp note x1 x2 regc regoff v dd v ss system control (regulator) a16 to a19
96 chapter 1 features of 78k/iv series products 1.17 product outline of m pd784955 subseries ( m pd784953, 784955, 78f4956) 1.17.1 features ? minimum instruction execution time: 160 ns (at f clk = 12.5-mhz operation) ? on-chip memory ? rom mask rom : 24 kbytes ( m pd784953) 48 kbytes ( m pd784955) flash memory : 64 kbytes ( m pd78f4956) ? ram : 768 bytes ( m pd784953) : 2,048 bytes ( m pd784955, 78f4956) ? i/o port : 67 ? timer/counter: 16-bit timer/counter 6 units 8-bit timer/counter 2 units ? serial interface: 2 channels uart: 1 channel (on-chip baud rate generator) csi (3-wire serial i/o): 1 channel ? a/d converter: 8-bit resolution 8 channels ? real-time output function: 6-bit resolution 2 channels ? watchdog timer: 1 channel ? standby function halt/stop/idle mode low power consumption mode: halt/idle mode (subsystem clock operation) ? interrupt controller (4-level priority) vector interrupt/macro service/context switching ? power supply voltage: v dd = 4.5 to 5.5 v 1.17.2 applications motor control for inverter air conditioners, etc.
97 chapter 1 features of 78k/iv series products 1.17.3 ordering information and quality grade (1) ordering information part number package internal rom m pd784935gc- -8bt 80-pin plastic qfp (14 14 mm) mask rom m pd784955gc- -8bt 80-pin plastic qfp (14 14 mm) mask rom m pd78f4956gc-8bt 80-pin plastic qfp (14 14 mm) flash memory remark indicates rom code suffix. (2) quality grades part number package quality grade m pd784935gc- -8bt 80-pin plastic qfp (14 14 mm) standard m pd784955gc- -8bt 80-pin plastic qfp (14 14 mm) standard m pd78f4956gc-8bt 80-pin plastic qfp (14 14 mm) standard please refer to quality grades on nec semiconductor devices (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. remark indicates rom code suffix. caution the m pd784955 subseries is under development.
98 chapter 1 features of 78k/iv series products 1.17.4 outline of functions product name m pd784953 m pd784955 m pd78f4956 item number of basic instructions (mnemonics) 113 general registers 8 bits 16 registers 8 banks or 16 bits 8 registers 8 banks (memory mapped) minimum instruction execution time 160 ns (at f clk = 12.5-mhz operation) internal memory capacity rom 24 kbytes 48 kbytes 64 kbytes (mask rom) (mask rom) (flash memory) ram 768 bytes 2,048 bytes i/o port total 67 cmos input 8 cmos i/o 59 additional pin with pull-up 59 function pin note resistor led direct drive output 32 real-time output port 6 bits 2 timer/counter 16-bit timer/counter: timer register 1 pulse output capability capture/compare register 2 ? pwm output 16-bit timer/counter 1: timer register 1 pulse output capability compare register 2 ? pwm output 16-bit timer/counter 2: timer register 1 pulse output capability compare register 2 ? pwm output 16-bit timer/counter 3: timer register 1 compare register 2 16-bit timer/counter 4: timer register 1 capture/compare register 3 16-bit timer/counter 5: timer register 1 compare register 1 capture/compare register 2 8-bit timer/counter 6: timer register 1 pulse output capability compare register 1 ? pwm output 8-bit timer/counter 7: timer register 1 compare register 1 serial interface ? uart: 1 channel (on-chip baud rate generator) ? csi (3-wire serial i/o): 1 channel a/d converter 8-bit resolution 8 channels watchdog timer 1 channel standby function halt/stop/idle mode note the pins with additional functions are included in the i/o pins. (1/2)
99 chapter 1 features of 78k/iv series products product name m pd784953 m pd784955 m pd78f4956 item interrupt hardware sources 28 (internal: 22, external: 8 (shared with internal: 2)) software sources brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 20, external: 7 ? 4-level programmable priority ? 3 processing modes: vectored interrupt, macro service, context switching power supply voltage v dd = 4.5 to 5.5 v package 8 0-pin plastic qfp (14 14 mm) (2/2)
100 chapter 1 features of 78k/iv series products 1.17.5 block diagram programmable interrupt controller uart intp0 to intp6 intp0 intp1 to0 intp2 intp3 intp4 intp5 intp6 intp3 intp5 rtp02 to rtp07 rtp12 to rtp17 ani0 to ani7 intp0 av dd av ss av ref to6 to1 to2 baud-rate generator clocked serial interface system control real-time outputport0 real-time outputport1 a/d converter timer/counter (16bits) timer/counter1 (16bits) timer/counter2 (16bits) rom ram timer/counter3 (16bits) timer/counter4 (16bits) timer/counter5 (16bits) timer/counter6 (8bits) timer/counter7 (8bits) watchdogtimer 78k/iv cpu core bus i/f port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port9 rxd txd rd p00 to p07 p10 to p17 p20, p21, p25 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p67 p70 to p77 p90 to p95 reset x1 x2 v dd v ss ic/v pp note wr si so sck note in the flash memory programming mode of the m pd78f4956. remark internal rom and ram capacities vary depending on the products.
101 chapter 2 memory space 2.1 memory space the 78k/iv series can access a maximum memory space of 16 mbytes. however, memory mapping varies from product to product according to the on-chip memory capacity and pin status. therefore, the users manual hardware for the individual products should be consulted for details of the memory map address areas. the 78k/iv series can access a 16-mbyte memory space. the mapping of the internal data area (special function registers and internal ram) depends on the location instruction. a location instruction must be executed after reset release, and can only be used once. the program after reset release must be as follows. rstvct cseg at 0 dw rststrt initseg cseg base rststrt:location 0h; or location 0fh movg sp, #stkbgn (1) when location 0 instruction is executed the internal data area is mapped with the maximum address as ffffh. an area in the internal rom that overlaps an internal data area cannot be used as internal rom when the location 0 instruction is executed. external memory is accessed in external memory extension mode. (2) when location 0fh instruction is executed the internal data area is mapped with the maximum address as fffffh. the m pd784915 subseries is fixed to the location 0 instruction. ~
102 chapter 2 memory space figure 2-1. memory map when location 0 instruction is executed ffffffh 100000h 0fffffh 010000h 00ffffh 000fffh 000800h 00007fh 000040h 00003fh 000000h data space (15 mbytes) program/data space (1 mbyte) memory space (16 mbytes) internal rom area internal data area internal rom area callf entry area vector table area callt table area 00ffffh 00ffdfh 00ffd0h 00ff00h 00feffh 00fe80h 00fe3bh 00fe06h 00fd00h special function registers (sfr) (256 bytes) general register area (128 bytes) macro service control word area internal ram area internal high-speed ram (512 bytes) data area internal peripheral ram program/data area 0fffffh 0fffdfh 0fffd0h 0fff00h 0ffeffh 0ffe80h 0ffe3bh 0ffe06h 0ffd00h ffffffh 100000h 0fffffh 010000h 00ffffh 000fffh 000800h 00007fh 000040h 00003fh 000000h when location 0fh instruction is executed internal data area internal rom area callf entry area callt table area vector table area data space (15 mbytes) base area program/data space (1 mbyte) memory space (16 mbytes) base area note note external sfr area caution the m pd784915 subseries is fixed to the location 0 instruction.
103 chapter 2 memory space 2.2 internal rom area the 78k/iv series products shown below incorporate rom which is used to store programs, table data, etc. if the internal rom area and internal data area overlap when the location 0 instruction is executed, the internal data area is accessed, and the overlapping part of the internal rom area cannot be accessed. the m pd784915 subseries is fixed to the location 0 instruction. table 2-1. list of internal rom space for 78k/iv series products (1/2) subseries name product address space internal rom m pd784026 subseries m pd784020 none m pd784021 m pd784025 00000h to 0bfffh 48 k 8 bits m pd784026 00000h to 0ffffh 64 k 8 bits m pd78p4026 m pd784038 subseries m pd784031 none m pd784038y subseries m pd784031y m pd784035 00000h to 0bfffh 48 k 8 bits m pd784035y m pd784036 00000h to 0ffffh 64 k 8 bits m pd784036y m pd784037 00000h to 17fffh 96 k 8 bits m pd784037y m pd784038 00000h to 1ffffh 128 k 8 bits m pd78p4038 m pd784038y m pd78p4038y m pd784046 subseries m pd784044 00000h to 07fffh 32 k 8 bits m pd784054 m pd784046 00000h to 0ffffh 64 k 8 bits m pd78f4046 m pd784216 subseries m pd784214 00000h to 17fffh 96 k 8 bits m pd784216y subseries m pd784214y m pd784215 00000h to 1ffffh 128 k 8 bits m pd784215y m pd784216 m pd784216y m pd78f4216 m pd78f4216y m pd784218 subseries m pd784217 00000h to 2ffffh 192 k 8 bits m pd784218y subseries m pd784217y m pd784218 00000h to 3ffffh 256 k 8 bits m pd784218y m pd78f4218 m pd78f4218y remark in case of a rom-less product, this address space is an external memory.
104 chapter 2 memory space table 2-1. list of internal rom space for 78k/iv series products (2/2) subseries name product address space internal rom m pd784225 subseries m pd784224 00000h to 17fffh 96 k 8 bits m pd784225y subseries m PD784224Y m pd784225 00000h to 1ffffh 128 k 8 bits m pd784225y m pd78f4225 m pd78f4225y m pd784908 subseries m pd784907 00000h to 17fffh 96 k 8 bits m pd784908 00000h to 1ffffh 128 k 8 bits m pd78p4908 m pd784915 subseries m pd784915 00000h to 0bfffh 48 k 8 bits m pd784915a m pd784916a 00000h to 0f6ffh 62 k 8 bits m pd78p4916 m pd784928 subseries m pd784927 00000h to 17fffh 96 k 8 bits m pd784928y subseries m pd784927y m pd78f4928 00000h to 1ffffh 128 k 8 bits m pd78f4928y m pd784937 subseries m pd784935 00000h to 17fffh 96 k 8 bits m pd784936 00000h to 1ffffh 128 k 8 bits m pd784937 00000h to 2ffffh 192 k 8 bits m pd78f4937 m pd784955 subseries m pd784953 00000h to 05fffh 24 k 8 bits m pd784955 00000h to 0bfffh 48 k 8 bits m pd78f4956 00000h to 0f6ffh 64 k 8 bits
105 chapter 2 memory space 2.3 base area the space from 00000h to fffffh comprises the base area. the base area is the object for the following uses. ? reset entry address ? interrupt entry address ? callt instruction entry address ? 16-bit immediate addressing mode (with instruction address addressing) ? 16-bit direct addressing mode ? 16-bit register addressing mode (with instruction address addressing) ? 16-bit register indirect addressing mode ? short direct 16-bit memory indirect addressing mode the vector table area, callt instruction table area and callf instruction entry area are allocated to the base area. when the location 0 instruction is executed, the internal data area is located in the base area. note that, in the internal data area, program fetches cannot be performed from the internal high-speed ram area and special function register (sfr) area. also, internal ram area data should only be used after initialization has been performed.
106 chapter 2 memory space 2.3.1 vector table area the 64-byte area from 00000h to 0003fh is reserved as the vector table area. the vector table area holds the program start addresses used when a jump is performed as the result of reset input or generation of an interrupt request. when context switching is used by an interrupt, the number of the register bank to be switched to is stored here. any portion not used by the vector table can be used as program memory or data memory. 16-bit values can be written to the vector table. therefore, branches can only be made within the base area. table 2-2. vector table vector table address interrupts 00000h reset (reset input) 00002h nmi note 00004h wdt note 00006h to differs for each product 0003ah 0003ch operand error interrupt 0003eh brk note not used by some products. 2.3.2 callt instruction table area the 1-byte call instruction (callt) subroutine entry addresses can be stored in the 64-byte area from 00040h to 0007fh. the callt instruction references this table, and branches to a base area address written in the table as a subroutine. as the callt instruction is one byte in length, use of the callt instruction for subroutine calls written frequently throughout the program enables the program object size to be reduced. the table can contain up to 32 subroutine entry addresses, and therefore it is recommended that they be recorded in order of frequency. if this area is not used as the callt instruction table, it can be used as ordinary program memory or data memory. values that can be written to the callt instruction table are 16-bit values. therefore, a branch can only be made within the base area. 2.3.3 callf instruction entry area a subroutine call can be made directly to the area from 00800h to 00fffh with the 2-byte call instruction (callf). as the callf instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of the direct subroutine call call instruction (3 bytes). writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device. if you wish to reduce the object size, writing an unconditional branch (br) instruction in this area and locating the subroutine itself outside this area will result in a reduced object size for subroutines that are called from five or more points. in this case, only the 4 bytes of the br instruction are occupied in the callf entry area, enabling the object size to be reduced with a large number of subroutines.
107 chapter 2 memory space 2.4 internal data area the internal data area comprises the internal ram area and special function register area. in some products, memories dependent on other hardware are also allocated to this areas (see the users manual hardware of each product). the final address of the internal data area can be specified by means of the location instruction as either ffffh (when a location 0 instruction is executed) or fffffh (when a location 0fh instruction is executed). selection of the addresses of the internal data area by means of the location instruction must be executed once immediately after reset release, and once the selection is made, it cannot be changed. the program after reset release must be as shown in the example below. if the internal data area and another area are allocated to the same addresses, the internal data area is accessed and the other area cannot be accessed. example rstvct cseg at 0 dw rststrt initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn cautions 1. when the location 0 instruction is executed, it is necessary to ensure that the program after reset release does not overlap the internal data area. it is also necessary to make sure that the entry addresses of the service routines for non-maskable interrupts such as nmi do not overlap the internal data area. also, initialization must be performed for maskable interrupt entry areas, etc., before the internal data area is referenced. 2. the m pd784915 subseries is fixed to the location 0 instruction. 2.4.1 internal ram area 78k/iv series products incorporate general-purpose static ram. this area is configured as follows: peripheral ram (pram) ? internal ram area internal high-speed ram (iram) ~
108 chapter 2 memory space table 2-3. internal ram area in 78k/iv series products (1/2) subseries name product internal ram area peripheral ram: pram internal high-speed ram: iram m pd784026 subseries m pd784020 512 bytes 0 byte 512 bytes (0fd00h to 0feffh) (0fd00h to 0feffh) m pd784021 2,048 bytes 1,536 bytes m pd784025 (0f700h to 0feffh) (0f700h to 0fcffh) m pd784026 m pd78p4026 m pd784038 subseries m pd784031 2,048 bytes 1,536 bytes m pd784038y subseries m pd784031y (0f700h to 0feffh) (0f700h to 0fcffh) m pd784035 m pd784036 m pd784035y m pd784036y m pd784037 3,584 bytes 3,072 bytes m pd784037y (0f100h to 0feffh) (0f100h to 0fcffh) m pd784038 4,352 bytes 3,840 bytes m pd78p4038 (0ee00h to 0feffh) (0fe00h to 0fcffh) m pd784038y m pd78p4038y m pd784046 subseries m pd784044 1,024 bytes 512 bytes m pd784045 (0fb00h to 0feffh) (0fb00h to 0fcffh) m pd784046 2,048 bytes 1,536 bytes m pd78f4046 (0f700h to 0feffh) (0f700h to 0fcffh) m pd784216 subseries m pd784214 3,584 bytes 3,072 bytes m pd784216y subseries m pd784214y (0f100h to 0feffh) (0f100h to 0fcffh) m pd784215 5,120 bytes 4,608 bytes m pd784215y (0eb00h to 0feffh) (0fb00h to 0fcffh) m pd784216 8,192 bytes 7,680 bytes m pd784216y (0df00h to 0feffh) (0df00h to 0fcffh) m pd78f4216 m pd78f4216y m pd784218 subseries m pd784217 12,800 bytes 12,288 bytes m pd784218y subseries m pd784217y (0cd00h to 0feffh) (0cd00h to 0fcffh) m pd784218 m pd784218y m pd78f4218 m pd78f4218y m pd784225 subseries m pd784224 3,584 bytes 3,072 bytes m pd784225y subseries m PD784224Y (0f100h to 0feffh) (0cf10h to 0fcffh) m pd784225 4,352 bytes 3,840 bytes m pd784225y (0ee00h to 0feffh) (0ee00h to 0fcffh) m pd78f4225 m pd78f4225y remark the addresses in the table are the values that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above.
109 chapter 2 memory space table 2-3. internal ram area in 78k/iv series products (2/2) subseries name product internal ram area peripheral ram: pram internal high-speed ram: iram m pd784908 subseries m pd784907 3,584 bytes 3,072 byte 512 bytes (0f100h to 0feffh) (0f100h to 0feffh) (0fd00h to 0feffh) m pd784908 4,352 bytes 3,840 bytes m pd78p4908 (0ee00h to 0feffh) (0ee00h to 0fcffh) m pd784915 subseries m pd784915 1,280 bytes 768 bytes m pd784915a (0fa00h to 0feffh) (0fa00h to 0fcffh) m pd784916a m pd78p4916 2,048 bytes 1,536 bytes (0f700h to 0feffh) (0f700h to 0fcffh) m pd784928 subseries m pd784927 2,048 bytes 1,536 bytes m pd784928y subseries m pd784927y (0f700h to 0feffh) (0f700h to 0fcffh) m pd78f4928 3,584 bytes m pd78f4928y (0f100h to 0feffh) m pd784937 subseries m pd784935 5,120 bytes 4,608 bytes (0eb00h to 0feffh) (0eb00h to 0fcffh) m pd784936 6,656 bytes 6,144 bytes (0e500h to 0feffh) (0e500h to 0fcffh) m pd784937 8,192 bytes 7,680 bytes m pd78f4937 (0df00h to 0feffh) (0df00h to 0fcffh) m pd784955 subseries m pd784953 768 bytes 256 bytes (0fc00h to 0feffh) (0fc00h to 0fcffh) m pd784955 2,048 bytes 1,536 bytes m pd78f4956 (0f700h to 0feffh) (0f700h to 0fcffh) remark the addresses in the table are the values that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. the m pd784915 subseries is fixed to the location 0 instruction.
110 chapter 2 memory space internal ram mapping is shown in figure 2-2. figure 2-2. internal ram memory mapping remark the addresses in the figure are the values that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown above. the m pd784915 subseries is fixed to the location 0 instruction. 00feffh 00fe80h 00fe3bh 00fe04h 00fe00h 00fdffh 00fd00h 00fcffh differs according to product 00fd20h 00fd1fh general register area macro service control word area peripheral ram short direct addressing 1 permissible range short direct addressing 2 permissible range internal high-speed ram
111 chapter 2 memory space (1) internal high-speed ram (iram) the internal high-speed ram (iram) allows high-speed accesses to be made. the short direct addressing mode for high-speed accesses can be used on 0fd20h to 0feffh in this area. there are two kinds of short direct addressing mode, short direct addressing 1 and short direct addressing 2, according to the target address. the function is the same in both of these addressing modes. with some instructions, the word length is shorter with short direct addressing 2 than with short direct addressing 1. see chapter 6 instruction set for details. a program fetch cannot be performed from iram. if a program fetch is performed from an address onto which iram is mapped, cpu runaway will result. the following areas are reserved in iram. ? general register area : 0fe80h to 0feffh ? macro service control word area : 0fe06h to 0fe3bh (the addresses actually reserved differ from product to product) ? macro service channel area : 0fe00h to 0feffh (the address is specified by the macro service control word) if the reserved function is not used in these areas, they can be used as ordinary data memory. remark the addresses in this text are those that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown. the m pd784915 subseries is fixed to the location 0 instruction. (2) peripheral ram (pram) the peripheral ram (pram) is used as ordinary program memory or data memory. when used as program memory, he program must be written to the peripheral ram beforehand by a program.
112 chapter 2 memory space 2.4.2 special function register (sfr) area the on-chip peripheral hardware special function registers (sfrs) are mapped onto the area from 0ff00h to 0ffffh (see the users manual hardware for the individual products). in some products, the area from 0ffd0h to 0ffdfh is mapped as an external sfr area, and allows externally connected peripheral i/os, etc., to be accessed in external memory extension mode (specified by the memory extension mode register (mm)) by rom-less products or on-chip rom products. caution addresses onto which sfrs are not mapped should not be accessed in this area. if such an address is accessed by mistake, the cpu may become deadlocked. a deadlock can only be released by reset input. remark the addresses in this text are those that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the values shown. the m pd784915 subseries is fixed to the location 0 instruction. 2.4.3 external sfr area in some 78k/iv series products, the 16-byte area from 0ffd0h to 0ffdfh in the sfr area (when the location 0 instruction is executed; 0fffd0h to 0fffdfh when the location 0fh instruction is executed) is mapped as an external sfr area. when the external memory extension mode is set in a rom-less product or on-chip rom product, externally connected peripheral i/os, etc., can be accessed using the address bus or address/data bus, etc. as the external sfr area can be accessed by sfr addressing, peripheral i/o and similar operations can be performed easily, the object size can be reduced, and macro service can be used. bus operations for accesses to the external sfr area are performed in the same way as for ordinary memory accesses. 2.5 external memory space the external memory space is a memory space that can be accessed in accordance with the setting of the memory extension mode register (mm). it can hold programs, table data, etc., and can have peripheral i/o devices allocated to it. a program cannot be allocated to the area from 100000h to 0ffffffh in the external memory space. note also that some products do not have an external memory space.
113 chapter 3 registers 3.1 control registers control registers consist of the program counter (pc), program status word (psw), and stack pointer (sp). 3.1.1 program counter (pc) this is a 20-bit binary counter that holds information on the next program address to be executed (see figure 3- 1 ). normally, the pc is incremented automatically by the number of bytes in the fetched instruction. when an instruction associated with a branch is executed, the immediate data or register contents are set in the pc. upon reset input, the 16-bit data in address 0 and address 1 is set in the low-order 16 bits of the pc, and 0000 in the high-order 4 bits. figure 3-1. program counter (pc) configuration 3.1.2 program status word (psw) the program status word (psw) is a 16-bit register comprising various flags that are set or reset according to the result of instruction execution. read accesses and write accesses are performed in high-order 8-bit (pswh) and low-order 8-bit (pswl) units. individual flags can be accessed by bit-manipulation instructions. the contents of the psw are automatically saved to the stack when a vectored interrupt request is acknowledged or a brk instruction is executed, and automatically restored when an reti or retb instruction is executed. when context switching is used, the contents are automatically saved in rp3, and automatically restored when an retcs or retcsb instruction is executed. reset input resets (0) all bits. 0 must always be written to the bits written as 0 in figure 3-2. the contents of bits written as C are undefined when read. pc 19 0
114 chapter 3 registers figure 3-2. program status word (psw) configuration the flags are described below. (1) carry flag (cy) the carry flag stores a carry or borrow resulting from an operation. this flag also stores the shifted-out value when a shift/rotate instruction is executed, and functions as a bit accumulator when a bit-manipulation instruction is executed. the status of the cy flag can be tested with a conditional branch instruction. (2) parity/overflow flag (p/v) the p/v flag performs the following two kinds of operation associated with execution of an operation instruction. the status of the p/v flag can be tested with a conditional branch instruction. ? parity flag operation set (1) when the number of bits set (1) as the result of execution of a logical operation instruction, shift/ rotate instruction, or a chkl or chkla instruction is even, and reset (0) if odd. when a 16-bit shift instruction is executed, however, only the low-order 8 bits of the operation result are valid for the parity flag. ? overflow flag operation set (1) when the numeric range expressed as a twos complement is exceeded as the result of execution of a logical operation instruction, and reset (0) otherwise. more specifically, the value of this flag is the exclusive or of the carry into the msb and the carry out of the msb. for example, the twos complement range in an 8-bit arithmetic operation is 80h (C128) to 7fh (+127), and the flag is set (1) if the operation result is outside this range, and reset (0) if within this range. 76 543 2 10 uf rbs2 rbs1 rbs0 pswh 76 543 2 10 s z rss ac ie p/v 0 cy pswl
115 chapter 3 registers example the operation of the overflow flag when an 8-bit addition instruction is executed is shown below. when the addition of 78h (+120) and 69h (+105) is performed, the operation result is e1h (+225), and the twos complement limit is exceeded, with the result that the p/v flag is set (1). expressed as a twos complement, e1h is C31. 78h (+120) = 0111 1000 +) 69h (+105) = +) 0110 1001 0 1110 0001 = C31 p/v = 1 - cy when the following two negative numbers are added together, the operation result is within the twos complement range, and therefore the p/v flag is reset. fbh (C5) = 1111 1011 +) f0h (C16) = +) 1111 0000 1 1110 1011 = C21 p/v = 0 - cy (3) interrupt request enable flag (ie) this flag controls cpu interrupt request acknowledgment operations. when 0, interrupts are disabled, and only non-maskable interrupts and unmasked macro service requests can be acknowledged. all other interrupts are disabled. when 1, the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts. the ie flag is set (1) by execution of an ei instruction, and reset (0) by execution of a di instruction or acknowledgment of an interrupt. (4) auxiliary carry flag (ac) the ac flag is set (1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset (0) otherwise. this flag is used when the adjba or adjbs instruction is executed. (5) register set selection flag (rss) the rss flag specifies the general registers that function as x, a, c, and b, and the general register pairs (16-bit) that function as ax and bc. this flag is provided to maintain compatibility with the 78k/iii series, and must be set to 0 except when using a 78k/iii series program.
116 chapter 3 registers (6) zero flag (z) the z flag records that the result of an operation is 0. it is set (1) when the result of an operation is 0, and reset (0) otherwise. the status of the z flag can be tested with a conditional branch instruction. (7) sign flag (s) the s flag records that the msb is 1 as the result of an operation. it is set (1) when the msb is 1 as the result of an operation, and reset (0) otherwise. the status of the s flag can be tested with a conditional branch instruction. (8) register bank selection flag (rbs0 to rbs2) this is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (see table 3-1 ). it holds 3-bit information which indicates the register bank selected by execution of a sel rbn instruction, etc. table 3-1. register bank selection rbs2 rbs1 rbs0 specified register bank 0 0 0 register bank 0 0 0 1 register bank 1 0 1 0 register bank 2 0 1 1 register bank 3 1 0 0 register bank 4 1 0 1 register bank 5 1 1 0 register bank 6 1 1 1 register bank 7 (9) user flag (uf) this flag can be set and reset in the user program, and used for program control.
117 chapter 3 registers 3.1.3 use of rss bit basically, the rss bit should be fixed at 0 at all times. the following explanation refers to the case where a 78k/iii series program is used, and the program used sets the rss bit to 1. this explanation can be skipped if the rss bit is fixed at 0. the rss bit is provided to allow the functions of a (r1), x (r0), b (r3), c (r2), ax (rp0), and bc (rp1) to be used by registers r4 to r7 (rp2, rp3) as well. effective use of this bit enables efficient programs to be written in terms of program size and program execution. however, careless use can result in unforeseen problems. therefore, the rss bit should always be set to 0. the rss bit should only be set to 1 when a 78k/iii series program is used. use of the rss bit set to 0 in all programs will improve programming and debugging efficiency. even when using a program in which the rss bit is used set to 1, it is recommended that the program be amended if possible so that it does not set the rss bit to 1. (1) rss bit functions ? registers used by instructions for which the a, x, b, c, and ax registers are directly entered in the operand column of the instruction operation list (see 6.2 .) ? registers specified as implied by instructions that use the a, ax, b, and c registers by means of implied addressing ? registers used in addressing by instructions that use the a, b, and c registers in indexed addressing and based indexed addressing the registers used in these cases are switched as follows according to the rss bit. C when rss = 0 a ? r1, x ? r0, b ? r3, c ? r2, ax ? rp0, bc ? rp1 C when rss = 1 a ? r5, x ? r4, b ? r7, c ? r6, ax ? rp2, bc ? rp3
118 chapter 3 registers registers used other than those mentioned above are always the same irrespective of the value of the rss bit. with the nec assembler (ra78k4), the register operation code generated when the a, x, b, c, ax, and bc registers are described by those names is determined by the assembler rss pseudo-instruction. when the rss bit is set or reset, an rss pseudo-instruction must be written immediately before (or immediately after) the relevant instruction (see example below). ? when rss is set to 0 rss 0 ; rss pseudo-instruction clr1 pswl.5 mov b, a ; this description is equivalent to mov r3, r1. ? when rss is set to 1 rss 1 ; rss pseudo-instruction set1 pswl.5 mov b, a ; this description is equivalent to mov r7, r5. (2) operation code generation method with ra78k4 ? with ra78k4, if there is an instruction with the same function as an instruction for which a or ax is directly entered in the operand column of the instruction operation list, the operation code for which a or ax is directly entered in the operand column is generated first. example the function is the same when b is used for r in a mov a, r instruction and when a is used as r and b is used as r in a mov r, r instruction, and the same description (mova, b) is used in the assembler source program. in this case, ra78k4 generates code equivalent to the mov a, r instruction. remark the register that is actually used with this instruction is determined when the program is run according to the contents of the rss bit in the psw. when rss = 0, r1 or rp0 is used, and when rss = 1, r5 or rp2 is used.
119 chapter 3 registers ? if a, x, b, c, ax, or bc is written in an instruction for which r, r, rp and rp are specified in the operand column, the a, x, b, c, ax, and bc instructions generate an operation code that specifies the following registers according to the operand of the ra78k4 pseudo-instruction. register rss 0 rss 1 ar1r5 xr0r4 br3r7 cr2r6 ax rp0 rp2 bc rp1 rp3 ? if r0 to r7 or rp0 to rp4 is written as r, r, rp or rp in the operand column, an operation code in accordance with that specification is output (an operation code for which a or ax is directly entered in the operand column is not output.) ? descriptions r1, r3, r2 or r5, r7, r6 cannot be used for registers a, b, and c used in indexed addressing and based indexed addressing. (3) operating precautions switching the rss bit has the same effect as having two register sets. however, the following point must be noted. if use with rss = 1 is essential, these defects must be given full consideration when writing the program. (a) when writing a program, care must be taken to ensure that the static program description and dynamic rss bit changes at the time of program execution always coincide. for example, when an mov a, b instruction is assembled by ra78k4, mov a, r code is generated. in this case, the registers actually used are as shown below according to the rss pseudo-instruction written directly before the mov a, b instruction in the source program and the rss bit in the psw when the program is run. rss pseudo-instruction operand 01 rss bit in psw 0 mov r1, r3 mov r1, r7 1 mov r5, r3 mov r5, r7
120 chapter 3 registers (b) as a program that sets rss to 1 cannot be used by a program that uses the context switching function, program applicability is poor. (c) if interrupts are used by a program with more than one section in which the rss bit in the psw is set to 1, it is necessary to set the rss bit in the psw to 0 or 1 at the beginning of the interrupt service program, and write an rss pseudo-instruction corresponding to this in the source program. if this is not done, the execution results may sometimes be incorrect. for example, consider the following interrupt service program. int: push ax mov a, #byte add !!addr24, a pop ax reti in this program, the register determined at assembly time by the rss pseudo-instruction written immediately before is used as the ax or a register in the push ax, mov a, #byte, and pop ax instructions. however, in the add !!addr24, a instruction, the register used as the a register is determined by the value to which the interrupted program set the rss bit in the psw. therefore, either the expected value or an unexpected value may be stored in the memory specified by !!addr24. in this example, only the interrupt service program execution result is in error, but if, for example, the add instruction operands are reversed (add a, !!addr24), the contents of the register used by the interrupt program might be corrupted. since the phenomenon occurs in an irregular fashion with this kind of bug, it is extremely difficult to find the cause during debugging. (d) as different registers are used under the same name, program legibility is poor and debugging is difficult.
121 chapter 3 registers 3.1.4 stack pointer (sp) the stack pointer is a 24-bit register that holds the start address of the stack area (lifo type: 000000h to ffffffh) (see figure 3-3 ). it is used to address the stack area when subroutine processing or interrupt servicing is performed. the contents of the sp are decremented before a write to the stack area and incremented after a read from the stack area (see figures 3-4 and 3-5 ). the sp is accessed by special instructions. the sp contents are undefined after reset input, and therefore the sp must always be initialized by an initialization program directly after reset release (before a subroutine call or interrupt acknowledgment). in some products a number of bits at the high-order end of the sp are fixed at 0. please refer to the users manual hardware for the individual products for details. example sp initialization movg sp, #0fee0h;sp ? 0fee0h (when used from fedfh) figure 3-3. stack pointer (sp) configuration sp 23 0
122 chapter 3 registers figure 3-4. data saved to stack area push sfr instruction stack push sfrp instruction stack sp spC1 sp ? spe1 sp spe1 sp ? spe2 spe2 higher byte lower byte push psw instruction stack push rg instruction stack sp spe1 sp ? spe2 spe2 pswh 7 - pswh 4 undefined pswl sp spe1 sp ? spe3 spe2 spe3 higher byte middle byte lower byte call, callf, callt instruction stack sp spe1 sp ? spe3 spe2 spe3 undefined pc19-pc16 pc15-pc8 pc7-pc0 sp spe1 spe4 spe2 spe3 sp ? spe4 pswh 7 - pswh 4 pc19-pc16 vectored interrupt stack push post, pushu post instruction (in case of push ax, rp2, rp3) stack sp spe1 spe4 spe2 spe3 sp ? spe6 spe5 spe6 r7 r6 r5 r4 a x rp3 rp2 ax pswl pc15-pc8 pc7-pc0
123 chapter 3 registers figure 3-5. data restored from stack area note this 4-bit data is ignored. cautions 1. with stack addressing, the entire 16-mbyte space can be accessed but a stack area cannot be reserved in the sfr area or internal rom area. 2. the sp is undefined after reset input. moreover, non-maskable interrupts can still be acknowledged when the sp is in an undefined state. an unanticipated operation may therefore be performed if a non-maskable interrupt request is generated when the sp is in the undefined state directly after reset release. to avoid this risk, the program after reset release must be written as follows. the m pd784915 subseries is fixed to the location 0 instruction. pop sfr instruction stack pop sfrp instruction stack sp sp ? sp+1 sp sp+1 sp ? sp+2 - higher byte lower byte pop psw instruction stack pop rg instruction stack sp sp+1 sp ? sp+2 - - pswh 7 - pswh 4 e note pswl sp sp+2 sp ? sp+3 sp+1 - - higher byte middle byte lower byte ret instruction stack sp sp+2 sp ? sp+3 sp+1 - - e note pc19-pc16 pc15-pc8 pc7-pc0 sp sp+3 sp+2 - sp+1 - sp ? sp+4 - pswh 7 - pswh 4 pc19-pc16 reti, retb instruction stack pop post, popu post instruction (in case of pop ax, rp2, rp3) stack sp sp+5 sp+2 sp+4 - sp+3 - sp ? sp+6 - sp+1 - - r7 r6 r5 r4 a x rp3 rp2 ax pswl pc15-pc8 pc7-pc0
124 chapter 3 registers rstvct cseg at 0 dw rststrt initseg cseg base rststrt: location 0h; or location 0fh movg sp, #stkbgn ~
125 chapter 3 registers 3.2 general registers 3.2.1 configuration there are sixteen 8-bit general registers. also, two general registers can be used together as a 16-bit general register. in addition, four of the 16-bit general registers can be combined with an 8-bit register for address extension and used as 24-bit address specification registers. general registers other than the v, u, t, and w registers for address extension are mapped onto internal ram. these register sets are provided in 8 banks, and can be switched by means of software or the context switching function. upon reset input, register bank 0 is selected. the register bank used during program execution can be checked by reading the register bank selection flag (rbs0, rbs1, rbs2) in the psw. figure 3-6. general register configuration remark absolute names are shown in parentheses. 23 15 0 07 0 7 a (r1) x (r0) ax (rp0) b (r3) c (r2) bc (rp1) r5 r4 rp2 r7 r6 rp3 r9 r8 vp (rp4) r11 r10 up (rp5) d (r13) e (r12) de (rp6) h (r15) l (r14) hl (rp7) whl (rg7) v u t w tde (rg6) uup (rg5) vvp (rg4) 8 banks
126 chapter 3 registers figure 3-7. general register addresses note when the location 0 instruction is executed. when the location 0fh instruction is executed, 0f0000h should be added to the address values shown. the m pd784915 subseries is fixed to the location 0 instruction. caution r4, r5, r6, r7, rp2, and rp3 can be used as the x, a, c, b, ax, and bc registers respectively by setting the rss bit of the psw to 1, but this function should only be used when using a 78k/ iii series program. remark when the register bank is switched, and it is necessary to return to the original register bank, an sel rbn instruction should be executed after first saving the psw to the stack with a push psw instruction. when returning to the original register bank, if the stack location does not change the pop psw instruction should be used. when the register bank is changed by a vectored interrupt service program, etc., the psw is automatically saved to the stack when an interrupt is acknowledged and restored by an reti or retb instruction, so that, if only one register bank is used in the interrupt service program, only an sel rbn instruction need be executed, and execution of a push psw and pop w instruction is not necessary. example 1. when register bank 2 is specified push psw sel rb2 operations in register bank 2 pop psw operations in original register bank 2. when the register bank is specified by a vectored interrupt service program. int: sel rb5 operation in register bank 5 reti automatic return to original register bank . . . . . . . . . . . . rbnk0 rbnk1 rbnk2 rbnk3 rbnk4 rbnk5 rbnk6 rbnk7 feffh note fe80h note 7070 15 0 h (r15) (fh) d (r13) (dh) r11 (bh) r9 (9h) r7 (7h) r5 (5h) b (r3) (3h) a (r1) (1h) l (r14) (eh) e (r12) (ch) r10 (ah) r8 (8h) r6 (6h) r4 (4h) c (r2) (2h) x (r0) (0h) hl (rp7) (eh) de (rp6) (ch) up (rp5) (ah) vp (rp4) (8h) rp3 (6h) rp2 (4h) bc (rp1) (2h) ax (rp0) (0h) 8-bit processing 16-bit processing . . . .
127 chapter 3 registers 3.2.2 functions in addition to being manipulated as 8-bit units, the general registers can also be manipulated as 16-bit units by pairing two 8-bit registers. also, four of the 16-bit general registers can be combined with an 8-bit register for address extension and manipulated as 24-bit units. each register can be used in a general way for temporary storage of an operation result and as the operand of an inter-register operation instruction. the area from 0fe80h to 0feffh (when the location 0 is executed; 0ffe80h to 0ffeffh when the location 0fh instruction is executed) can be given an address specification and accessed as ordinary data memory irrespective of whether or not it is used as the general register area. as 8 register banks are provided in the 78k/iv series, efficient programs can be written by using different register banks for normal processing and processing in the event of an interrupt. the registers have the following specific functions. a (r1): ? register mainly used for 8-bit data transfers and operation processing. can be used in combination with all addressing modes for 8-bit data. ? can also be used for bit data storage. ? can be used as the register that holds the offset value in indexed addressing and based indexed addressing. x (r0): ? can be used for bit data storage. ax (rp0): ? register mainly used for 16-bit data transfers and operation processing. can be used in combination with all addressing modes for 16-bit data. axde: ? used for 32-bit data storage when a divux, macw, or macsw instruction is executed. b (r3): ? has a loop counter function, and can be used by the dbnz instruction. ? can be used as the register that holds the offset value in indexed addressing and based indexed addressing. ? used as the macw and macsw instruction data pointer.
128 chapter 3 registers c (r2): ? has a loop counter function, and can be used by the dbnz instruction. ? can be used as the register that holds the offset value in based indexed addressing. ? used as the counter in a string instruction and the sacw instruction. ? used as the macw and macsw instruction data pointer. rp2: ? used to save the low-order 16 bits of the program counter (pc) when context switching is used. rp3: ? used to save the high-order 4 bits of the program counter (pc) and the program status word (psw) (excluding bits 0 to 3 of pswh) when context switching is used. vvp (rg4): ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing, based addressing and based indexed addressing. uup (rg5): ? has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means of the pushu and popu instructions. ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. de (rp6), hl (rp7): ? operate as the registers that specify the offset value in indexed addressing and based indexed addressing. tde (rg6): ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. ? used as the pointer in a string instruction and the sacw instruction. whl (rg7): ? register used mainly for 24-bit data transfers and operation processing. ? has a pointer function, and operates as the register that specifies the base address in register indirect addressing and based addressing. ? used as the pointer in a string instruction and the sacw instruction. in addition to the function name that emphasizes the specific function of the register (x, a, c, b, e, d, l, h, ax, bc, vp, up, de, hl, vvp, uup, tde, whl), each register can also be described by its absolute name (r0 to r15, rp0 to rp7, rg4 to rg7). the correspondence between these names is shown in table 3-2.
129 chapter 3 registers table 3-2. function names and absolute names (a) 8-bit register function name rss = 0 rss = 1 note r0 x r1 a r2 c r3 b r4 x r5 a r6 c r7 b r8 r9 r10 r11 r12 e e r13 d d r14 l l r15 h h absolute name (b) 16-bit register function name rss = 0 rss = 1 note rp0 ax rp1 bc rp2 ax rp3 bc rp4 vp vp rp5 up up rp6 de de rp7 hl hl (c) 24-bit register absolute name function name rg4 vvp rg5 uup rg6 tde rg7 whl absolute name note rss should only be set to 1 when a 78k/iii series program is used. remark r8 to r11 have no function name.
130 chapter 3 registers 3.3 special function registers (sfr) these are registers to which a specific function is assigned, such as on-chip peripheral hardware mode registers, control registers, etc., and they are mapped onto the 256-byte space from 0ff00h to 0ffffh note . please refer to the individual product documentation for details of the special function registers. note when the location 0 instruction is executed. when the location 0fh instruction is executed, the area is 0fff00h to 0fffffh. the m pd784915 subseries is fixed to the location 0 instruction. caution addresses onto which sfrs are not mapped should not be accessed in this area. if such an address is accessed by mistake, the cpu may become deadlocked. a deadlock can only be released by reset input.
131 chapter 4 interrupt functions the three kinds of processing shown in table 4-1 can be programmed as servicing for interrupt requests. multiprocessing control using a 4-level priority system can easily be performed for maskable vectored interrupts. table 4-1. interrupt request servicing service mode service performed by service pc/psw contents vectored interrupts software executed by branching to service routine associated saving to & restoration (any service contents) from stack context switching executed by automatic switching of associated saving to & restoration register bank and branching to service from fixed area in register bank routine (any service contents) macro service firmware execution of memory-i/o data transfers, no change etc. (fixed service contents) remark please refer to the users manual hardware for the individual products for details.
132 chapter 4 interrupt functions 4.1 kinds of interrupt request there are three kinds of interrupt request, as follows: ? software interrupt requests ? non-maskable interrupt requests ? maskable interrupt requests 4.1.1 software interrupt requests an interrupt request by software is generated when a brk instruction or brkcs rbn instruction is executed, or if here is an error in an operand of an mov wdm, #byte instruction or mov stbc, #byte instruction, location instruction (operand error interrupt). interrupt requests by software are acknowledged even in the interrupt disabled (di) state, and are not subject to interrupt priority control. therefore, when an interrupt request is generated by software, a branch is made to the interrupt service routine unconditionally. to return from a brk instruction, an retb instruction is executed. to return from a brkcs rbn instruction service routine, a retcsb !addr16 instruction is executed. as an operand error interrupt is an interrupt generated if there is an error in an operand, processing is required for branching to the initialization program by a reset release after the necessary processing has been performed, etc. 4.1.2 non-maskable interrupt requests a non-maskable interrupt request is generated when a valid edge is input to the nmi pin or when the watchdog timer overflows. the provision of the nmi pin and watchdog timer functions varies from product to product. please refer to the users manual hardware for the individual products for details. non-maskable interrupt requests are acknowledged unconditionally, even in the interrupt disabled (di) state. also, they are not subject to interrupt priority control, and are of higher priority that any other interrupt. 4.1.3 maskable interrupt requests a maskable interrupt request is one subject to masking control according to the setting of the interrupt control register. in addition, acknowledgment enabling/disabling can be set for all maskable interrupts by means of the ie flag in the psw. the priority order for maskable interrupt requests when interrupt requests of the same priority are generated simultaneously is predetermined (default priority). also, multiprocessing can be performed with interrupt priorities divided into 4 levels in accordance with the specification of the interrupt control register. however, macro service requests are acknowledged without regard to priority control or the ie flag.
133 chapter 4 interrupt functions 4.2 interrupt service modes 4.2.1 vectored interrupts a branch is made to the service routine using the memory contents of the vector table address corresponding to the interrupt source as the branch destination address. the following operations are executed to enable the cpu to perform interrupt servicing. ? when branching : the cpu state (pc & psw contents) is saved to the stack. ? when returning : cpu statuses (pc & psw contents) are restored from the stack. the return from the service routine to the main routine is performed by an reti instruction (or an retb instruction in the case of a brk instruction or operand error interrupt). the branch destination address is restricted to the base area from 0000h to ffffh. please refer to the users manual hardware for the individual products for details of the vector table. 4.2.2 context switching the prescribed register bank is selected by hardware by generation of an interrupt request or execution of a brkcs rbn instruction. with this function, a branch is made to the vector address stored beforehand in the register bank, and at the same time the contents of the program counter (pc) and program status word (psw) are stacked in the register bank. the return from the service routine is performed by a retcs !addr16 instruction (or an retcsb !addr16 instruction in the case of a brkcs rbn instruction). the branch destination address is restricted to the base area from 0000h to ffffh. figure 4-1. context switching operation by interrupt request generation 0000b 7 transfer pc19-pc16 pc15-pc0 temporary register psw save 1 save 1 (temporary register bit 8 to 11) exchange 6 save 5 register bank n (n = 0 to 7) v u t w ax bc r5 r4 r7 r6 vp up de hl register bank switching (rbs0-rbs2 ? n ) 3 rss ? 0 ie ? 0 4 register bank (0 to 7)
134 chapter 4 interrupt functions 4.2.3 macro service function in macro service, cpu execution is temporarily suspended when an interrupt is acknowledged, and the service set by firmware is executed. since macro service is performed without the intermediation of the cpu, it is not necessary to save cpu statuses such as the pc and psw contents. this is therefore very effective in improving the cpu service time. please refer to the users manual hardware for the individual products for details of macro service.
135 chapter 5 addressing 5.1 instruction address addressing the instruction address is determined by the contents of the program counter (pc), and is normally incremented (by 1 for one byte) automatically in accordance with the number of bytes in the fetched instruction each time an instruction is executed. however, when an instruction associated with a branch is executed, branch address information is set in the pc and a branch performed by means of the addressing modes shown below. the following kinds of instruction address addressing are provided: ? (8-bit/16-bit) relative addressing ? (11-bit/16-bit/20-bit) immediate addressing ? table indirect addressing ? 16-bit register addressing ? 20-bit register addressing ? 16-bit register indirect addressing ? 20-bit register indirect addressing details of each kind of addressing are given in the following sections.
136 chapter 5 addressing 5.1.1 relative addressing [function] the value obtained by adding the 8-bit or 16-bit immediate data in the operation code (displacement value: jdisp8, jdisp16) to the start address of the next instruction is transferred to the program counter (pc), and a branch is made. the displacement value is treated as signed twos complement data (C128 to +127, C32,768 to +32,767), with the msb as the sign bit. this is performed when a call $!addr20, br $!addr20, br $addr20, or conditional branch instruction is executed (only 8-bit immediate data can be used in a conditional branch instruction). [explanatory diagrams] 8-bit relative addressing 16-bit relative addressing pc+b 19 0 x 19 0 + 876 s 19 0 pc jdisp8 . . . b = number of instruction bytes when s = 0, all bits of x are 0 when s = 1, all bits of x are 1 pc+b 19 0 19 0 + s 19 0 pc jdisp16 . . . b = number of instruction bytes
137 chapter 5 addressing 5.1.2 immediate addressing [function] the immediate data in the instruction word is transferred to the program counter (pc), and a branch is made. this is performed when a call !!addr20, br !!addr20, call !addr16, br !addr16, or callf !addr11 instruction is executed. in the case of a call !addr16 or br !addr16 instruction (16-bit immediate addressing), the high-order 4-bit address is fixed at 0, and a branch is made to the base area. in the case of the callf !addr11 instruction, the high-order 9-bit address is fixed at 000000001. [explanatory diagrams] 20-bit immediate addressing 16-bit immediate addressing pc 19 0 16 15 8 7 70 call or br high addr. low addr. middle addr. pc 19 0 16 15 8 7 70 call or br low addr. middle addr. 0000
138 chapter 5 addressing 11-bit immediate addressing [caution] as the branch destination of the br !addr16 instruction is restricted, it should only be used when using a 78k/0, 78k/i, 78k/ii, or 78k/iii series program. pc 19 0 87 70 callf fal 000000001 11 10 fah
139 chapter 5 addressing 5.1.3 table indirect addressing [function] the specific location table contents (branch destination address) addressed by the immediate data in the low-order 5 bits of the operation code are transferred to the low-order 16 bits of the program counter (pc), 0000 is transferred to the high-order 4 bits, and a branch is made (the branch destination address is restricted to the base area). this is performed when a callt [addr5] instruction is executed. [explanatory diagram] pc 19 0 87 0000 16 15 low addr. high addr. memory (table) effective address effective address + 1 23 0000000000000000 01 87 65 0 ta 0 7 111 54 0 ta operation code effective address =
140 chapter 5 addressing 5.1.4 16-bit register addressing [function] the contents of register rp (rp0 to rp7) specified by the instruction word are transferred to the low-order 16 bits of the program counter (pc), 0000 is transferred to the high-order 4 bits, and a branch is made (the branch destination address is restricted to the base area). this is performed when a br rp or call rp instruction is executed. [explanatory diagrams] [caution] as the branch destination of the br rp instruction is restricted, it should only be used when using a 78k/0, 78k/i, 78k/ii, or 78k/iii series program. if ax or bc is written for rp, with the nec ra78k4 assembler the object code generated depends on the rss pseudo-instruction written immediately before. 1 should be specified by the rss pseudo-instruction only when a 78k/iii series program is used (see 3.1.3 use of rss bit ). 5.1.5 20-bit register addressing [function] the contents of register rg (rg4 to rg7) specified by the instruction word are transferred to the program counter (pc), and a branch is made. the high-order 4 bits of rg should be set to 0000. this is performed when a br rg or call rg instruction is executed. [explanatory diagram] pc 19 0 87 0000 16 15 0 07 7 rp 7 0 07 0000 4 pc 19 0 87 16 15 07
141 chapter 5 addressing 5.1.6 16-bit register indirect addressing [function] the 2 consecutive bytes of data in the memory addressed by the contents of register rp (rp0 to rp7) specified by the instruction word are transferred to the low-order 16 bits of the program counter (pc), 0000 is transferred to the high-order 4 bits, and a branch is made (the branch destination address is restricted to the base area). this is performed when a br [rp] or call [rp] instruction is executed. [explanatory diagram] [caution] as the address that holds the branch destination address and the branch destination of the br [rp] instruction are restricted, it should only be used when using a 78k/iii series program. if ax or bc is written for rp, with the nec ra78k4 assembler the object code generated depends on the rss pseudo-instruction written immediately before. 1 should be specified by the rss pseudo-instruction only when a 78k/iii series program is used (see 3.1.3 use of rss bit ). 23 0 87 00000000 16 15 0 07 7 rp effective address = 19 0 87 0000 16 15 low addr. high addr. memory effective address + 1 effective address
142 chapter 5 addressing 5.1.7 20-bit register indirect addressing [function] the 3 consecutive bytes of data in the memory addressed by the contents of register rg (rp0 to rp7) specified by the instruction word are transferred to the program counter (pc), and a branch is made. the high-order 4 bits of the 3-byte data stored in the memory should be set to 0000. this is performed when a br [rg] or call [rg] instruction is executed. [explanatory diagram] 19 0 87 16 15 middle addr. memory effective address + 1 low addr. high addr. 0000 23 0 87 16 15 0 07 7 rg effective address = 07 pc effective address effective address + 2
143 chapter 5 addressing 5.2 operand address addressing the following methods are available for specifying the register, memory, etc., to be manipulated when an instruction is executed. ? implied addressing ? register addressing ? immediate addressing ? 8-bit direct addressing ? 16-bit direct addressing ? 24-bit direct addressing ? short direct addressing ? special function register (sfr) addressing ? short direct 16-bit memory indirect addressing ? short direct 24-bit memory indirect addressing ? stack addressing ? 24-bit register indirect addressing (including 24-bit register indirect addressing with auto-increment/auto- decrement) ? 16-bit register indirect addressing ? based addressing ? indexed addressing ? based indexed addressing details of each kind of addressing are given in the following sections.
144 chapter 5 addressing 5.2.1 implied addressing [function] this type of addressing automatically addresses registers in the register bank specified by the register bank selection flags (rbs2, rbs1, and rbs0). instructions that use implied addressing in the 78k/iv series instruction word are shown below. the a, ax, c, and b registers used by these instructions are affected by the rss bit in the psw. when rss = 0, r1, rp0, r2, and r2, respectively are accessed for the a, ax, c, and b registers, and when rss = 1, r5, rp2, r6, and r7 are accessed. rss should only be set to 1 when a 78k/iii series program is used (see 3.1.3 use of rss bit ). instruction registers specified by implied addressing mulu a register as multiplicand, ax register as that holds product muluw, mulw ax register as multiplicand and register that holds high-order 16 bits of product divuw ax register as register that holds dividend and quotient divux axde register as register that holds dividend and quotient macw, macsw axde register as register that holds result of sum of products operation, b and c registers as pointer registers that specify data adjba, adjbs a register as register that holds numeric value subject to decimal adjustment cvtbw a register as register that holds data before sign extension is performed, and ax register as register that holds result of sign extension chkla a register as register that holds result of comparison between pin level and port output latch ror4, rol4 a register as register that holds digit data subject to digit rotation (only low-order 4 bits are used) sacw, string instruction c register as data counter string instruction [operand format] as this is used automatically according to the instruction, there is no specific operand format. [description example] mulu r; in an 8-bit x 8-bit multiplication instruction, the product of the a register and r register are stored in the ax register. here, the a and ax registers are specified by implied addressing.
145 chapter 5 addressing 5.2.2 register addressing [function] this type of addressing accesses as an operand the general register specified by the register specification code in the instruction word in the register bank specified by the register bank selection flag (rbs2, rbs1, rbs0). register addressing is performed when an instruction with one of the operand formats shown below is executed. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format aa cc xx bb r x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7, r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7 r2 r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r3 v, u, t, w ax ax rp ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5), de(rp6), hl(rp7) rp1 ax(rp0), bc(rp1), rp2, rp3 rp2 vp(rp4), up(rp5), de(rp6), hl(rp7) whl whl rg vvp(rg4), uup(rg5), tde(rg6), whl(rp7) remarks 1. absolute names are shown in parentheses. 2. with an instruction (such as addw ax, #word) in which a, x, ax, b, or c is specified directly as the register addressing operand, the register used as a, x, ax, b, or c is determined by the rss bit in the psw when the instruction is executed. the rss bit in the psw should be set to 1 only when a 78k/iii series program is used (see 3.1.3 use of rss bit ). 3. if a, x, b, c, ax, or bc is written as an operand in an instruction in which r, r1, rp, or rp1 is specified as the register addressing operand, with the nec ra78k4 assembler the object code generated depends on the rss pseudo-instruction written immediately before. 1 should be specified in the rss pseudo-instruction operand only when a 78k/iii series program is used (see 3.1.3 use of rss bit ). [description example 1] ? general example mov a, r ? specific example mov a, c ; when the c register is selected as r [description example 2] ? general example incw rp ? specific example incw de ; when the de register pair is selected as rp
146 chapter 5 addressing 5.2.3 immediate addressing [function] this type of addressing has 8-bit data, 16-bit data and 24-bit data subject to manipulation in the operation code. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format byte label or 8-bit immediate data word label or 16-bit immediate data imm24 label or 24-bit immediate data [description example] ? general example add a, #byte ? specific example add a, #77h ; when 77h is used as byte
147 chapter 5 addressing 5.2.4 8-bit direct addressing [function] with this kind of addressing, the immediate data in the instruction word is the operand address and the memory to be manipulated is addressed. it is used with the movtblw instruction. memory from 0fe00h to 0feffh is addressed when a location 0 instruction is executed, and memory from 0ffe00h to 0ffeffh when a location 0fh instruction is executed. [operand format] performed when an instruction with the operands shown below is executed. identifier description format !addr8 label, or immediate data 0fe00h to 0feffh note note when the location 0 instruction is executed. when the location 0fh instruction is executed, the range is 0ffe00h to 0ffeffh. the m pd784915 subseries is fixed to the location 0 instruction. [description examples] ? general example movtblw !addr8, n ? specific example movtblw !0fe24h, n; when fe24h is used as addr8 [explanatory diagram] remark l depends on the location instruction. ? when location 0 instruction is executed : 0000 ? when location 0fh instruction is executed : 1111 23 0 87 0000 16 15 effective address 11111110 l op code low addr. 70 memory ?
148 chapter 5 addressing 5.2.5 16-bit direct addressing [function] this type of addressing addresses memory subject to manipulation with the immediate data in the instruction word as the operand address. the base area can be addressed. [operand format] performed when an instruction with the operand format shown below is executed. identifier description format addr16 label or 16-bit immediate data [description example] ? general example mov a, !addr16 ? specific example mov a, !0fe00h ; when fe00h is used as addr16 [explanatory diagram] [remarks] this kind of addressing should only be used when it is absolutely essential to reduce the execution time or object size, or when 78k/0, 78k/i, 78k/ii, or 78k/iii series software is used and program amendment is difficult. amendments may be necessary in order to make further use of a program that uses this kind of addressing. 23 0 87 00000000 16 15 effective address low addr. middle addr. 70 base area memory ? op code
149 chapter 5 addressing 5.2.6 24-bit direct addressing [function] this type of addressing addresses memory subject to manipulation with the immediate data in the instruction word as the operand address. the entire memory space can be addressed. [operand format] performed when an instruction with the operand format shown below is executed. identifier description format addr24 label or 24-bit immediate data [description example] ? general example mov a, !!addr24 ? specific example mov a, !!54fe00h ; when 54fe00h is used as addr24 [explanatory diagram] 0 16 15 23 effective address high addr. low addr. 70 memory ? op code middle addr. 87
150 chapter 5 addressing 5.2.7 short direct addressing [function] this type of addressing directly addresses memory subject to manipulation in a fixed space with the 8-bit immediate data in the instruction word. this kind of addressing can be used with most instructions, and allows various kinds of data to be manipulated using a small number of bytes and small number of clocks. with short direct addressing, the applicable address range varies according to the location instruction in the same way as the internal data area location addresses. when a location 0 instruction is executed, internal ram from 0fd20h to 0feffh and special function registers (sfrs) from 0ff00h to 0ff1fh can be accessed. when a location 0fh instruction is executed, internal ram from 0ffd20h to 0ffeffh and sfrs from 0fff00h to 0fff1fh can be accessed. ports frequently accessed in the program, timer/counter unit compare registers and capture registers are mapped onto the sfr area on which short direct addressing is used. these special function registers can be manipulated using a small number of bytes and small number of clocks. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format saddr label or immediate data 0fd20h to 0ff1fh saddr1 label or immediate data 0fe00h to 0feffh saddr2 label or immediate data 0fd20h to 0fdffh and 0ff00h to 0ff1fh saddrp label or immediate data 0fd20h to 0ff1eh saddrp1 label or immediate data 0fe00h to 0fefeh saddrp2 label or immediate data 0fd20h to 0fdffh and 0ff00h to 0ff1eh (if 0fdffh is specified, the high-order byte is 0fe00h) saddrg label or immediate data 0fd20h to 0fefdh saddrg1 label or immediate data 0fe00h to 0fefdh (during 24-bit manipulation) saddrg2 label or immediate data 0fd20h to 0fdffh (during 24-bit manipulation) remark the addresses in this table are those that apply when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h should be added to the values shown. the m pd784915 subseries is fixed to the location 0 instruction.
151 chapter 5 addressing [description example] ? general example mov saddr, saddr ? specific example mov 0fe30h, 0fe50h [explanatory diagram] remark l depends on the location instruction. ? when location 0 instruction is executed : 0000 ? when location 0fh instruction is executed : 1111 x is determined by the op code information and the value of saddr-offset. ? when saddr1 is specified by op code: 10 ? when saddr2 is specified by op code and saddr-offset is 20h to ffh: 01 ? when saddr2 is specified by op code and saddr-offset is 00h to 1fh: 11 0 16 15 23 effective address 70 short direct memory ? op code saddr?ffset 87 0000 20 19 l 111111 x 10 9
152 chapter 5 addressing 5.2.8 special function register (sfr) addressing function [function] this type of addressing addresses memory-mapped special function registers (sfrs) with the 8-bit immediate data in the instruction word. the space used by this kind of addressing varies according to the location instruction in the same way as the internal data area location addresses. when a location 0 instruction is executed, it is the 256-byte space from 0ff00h to 0ffffh, and when a location 0fh instruction is executed, it is the 256-byte space from 0fff00h to 0fffffh. however, sfrs mapped onto 0ff00h to 0ff1fh (when the location 0 instruction is executed; 0fff00h to 0fff1fh accessed by short direct addressing. remarks 1. with the nec assembler package (ra78k4), short direct addressing is automatically (forcibly) used for instructions on sfrs in addresses that can be accessed by short direct addressing. 2. the m pd784915 subseries is fixed to the location 0 instruction. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format sfr special function register name sfrp name of special function register for which 16-bit operation is possible [description example] ? general example mov sfr, a ? specific example mov pm0, a ; when pm0 is specified as sfr [explanatory diagram] 0 16 15 23 effective address 70 op code sfr?ffset 0000 11111111 87 l sfr remark l depends on the location instruction. ? when location 0 instruction is executed : 0000 ? when location 0fh instruction is executed : 1111
153 chapter 5 addressing 5.2.9 short direct 16-bit memory indirect addressing [function] this type of addressing addresses base area memory subject to manipulation with the contents of the two consecutive bytes of short direct memory addressed by the 8-bit bits of the operand address and the high-order 8 bits of the operand address set to 00000000. this addressing is used when an instruction with [saddrp] in an operand is executed. [operand format] performed when an instruction with the operand format shown below is executed. identifier description format [saddrp] [label, immediate data fd20h to fefeh note ] note when the location 0 instruction is executed. when the location 0fh instruction is executed, the range is ffd20h to ffefeh. the m pd784915 subseries is fixed to the location 0 instruction. [description example] ? general example xch a, [saddrp] ? specific example xch a, [0fea0h] ; when memory indicated by 2-byte data in addresses 0fea0h and 0fea1h is specified [explanatory diagram] 70 op code saddr?ffset 70 low addr. high addr. 23 effective address 00000000 16 15 8 7 0 memory short direct memory short direct addressing [remarks] this kind of addressing should only be used when it is absolutely essential to reduce the execution time or object size, or when 78k/0, 78k/i, 78k/ii, or 78k/iii series software is used and program amendment is difficult. amendments may be necessary in order to make further use of a program that uses this kind of addressing.
154 chapter 5 addressing 5.2.10 short direct 24-bit memory indirect addressing [function] this type of addressing addresses memory subject to manipulation with the contents of the 3 consecutive bytes of short direct memory addressed by the 8-bit immediate data in the instruction word as the operand address. this addressing is used when an instruction with [%saddrg] in an operand is executed. [operand format] performed when an instruction with the operand format shown below is executed. identifier description format [%saddrg] [%label, immediate data fd20h to fefdh note ] note when the location 0 instruction is executed. when the location 0fh instruction is executed, the range is 0ffd20h to 0ffefdh. the m pd784915 subseries is fixed to the location 0 instruction. [description example] ? general example xch a, [%saddrg] ? specific example xch a, [%0fea0h] ; when memory indicated by 3-byte data in addresses 0fea0h, 0fea1h and 0fea2h is specified [explanatory diagram] 70 op code saddr?ffset 70 low addr. high addr. 23 effective address 16 15 8 7 0 memory short direct memory short direct addressing middle addr.
155 chapter 5 addressing 5.2.11 stack addressing [function] this type of addressing indirectly addresses the stack area in accordance with the contents of the stack pointer (sp) and user stack pointer (uup). the sp is used automatically when a push or pop instruction is executed, when register saving/restoration is performed as the result of interrupt request generation, and when a subroutine call or return instruction is executed. the uup is used automatically when a pushu or popu instruction is executed. [description example] push de ; when the contents of the de register are saved to the stack using a push instruction when this instruction is executed, the sp is automatically decremented (by 2) and the contents of the de register are saved to the stack. [explanatory diagram] caution with stack addressing, the entire 16-mbyte space can be accessed but a stack area cannot be reserved in the sfr area or internal rom area. sp sp? sp ? sp? sp? d register contents e register contents stack area
156 chapter 5 addressing 5.2.12 24-bit register indirect addressing [function] this type of addressing addresses the memory to be manipulated with the contents of register rg (rg4 to rg7) specified by the register pair specification code in the instruction word in the register bank specified by the register bank selection flag (rbs2, rbs1, rbs0) as the operand address. the entire memory space can be addressed. in addition, register indirect addressing with auto-increment that increments (+1/+2/+3) the register for which an address specification was made after instruction execution and register indirect addressing with auto-decrement that decrements (C1/C2/C3) the register after instruction execution are provided. the increment and decrement values are determined by the size of data manipulated. this type of addressing is ideal for consecutive processing of multiple items of data. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format mem [tde], [whl], [tde+], [whl+], [tdeC], [whlC], [vvp], [uup] mem1 [tde], [whl], [tde+], [tdeC] mem2 [tde], [whl] mem3 [tde], [whl], [vvp], [uup] remark + after register name: with auto-increment C after register name: with auto-decrement [description example] ? general example mov a, mem ? specific example add a, [tde] ; when [tde] is specified as mem
157 chapter 5 addressing [explanatory diagram] 24-bit register indirect addressing register indirect addressing with auto-increment/decrement remark +/C + : with auto-increment C : with auto-decrement 1/2/3 1 : when data size is 1 byte 2 : when data size is 2 bytes (1 word) 3 : when data size is 3 bytes rg 23 0 23 0 memory effective address rg 23 0 23 0 memory effective address 1/2/3 +/
158 chapter 5 addressing 5.2.13 16-bit register indirect addressing [function] this type of addressing addresses the memory to be manipulated with the contents of register rp (rp0 to rp3) specified by the register specification code in the instruction word in the register bank specified by the register bank selection flag (rbs2, rbs1, rbs0) as the operand address. the base area memory space can be addressed. this type of addressing is only used with the ror4 and rol4 instructions, and is used when processing multiple consecutive bytes of bcd data. this addressing is provided to maintain compatibility with the 78k/iii series, and should only be used when using a 78k/iii series program. [operand format] performed when an instruction with the operand format shown below is executed. identifier description format mem3 [ax], [bc], [rp2], [rp3] [description example] ? general example ror4 mem3 ? specific example ror4 [bc] ; when [bc] is written as mem3 [explanatory diagram] 23 effective address 00000000 16 15 0 memory 15 0 rp
159 chapter 5 addressing 5.2.14 based addressing [function] with this type of addressing, register rg (rg4 to rg7) specified by the register specification code in the instruction word or the stack pointer (sp) in the register bank specified by the register bank selection flag (rbs2, rbs1, rbs0) addressed with the result of adding 8-bit immediate data to addition is performed with the offset data extended to 24 bits as a positive number. a carry from the 24th bit is ignored. the entire memory space can be addressed. this type of addressing is used when specific data is specified in an array in which one record consists of a number of bytes of data. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format mem [tde + byte], [whl + byte], [sp + byte], [vvp + byte], [uup + byte] mem1 [tde + byte], [whl + byte], [sp + byte], [vvp + byte], [uup + byte] [description example] ? general example and a, mem ? specific example and a, [tde+10h] ; when based addressing using the sum of register tde as mem and 10h is selected [explanatory diagram] 23 effective address 0 memory 70 23 0 rg + 8-bit offset data record start address ? whl+2 ? whl ? record start address ? whl + 2 manipulated with whl as record start address one record of array : specific data in each record mov a, [whl+2h]
160 chapter 5 addressing 5.2.15 indexed addressing [function] with this type of addressing, the 24-bit address data written as the operand in the instruction word is used as the index, and memory is addressed with the result of adding the contents of the register specified in the instruction word in the register bank specified by the register bank selection flag (rbs2, rbs1, rbs0) to this value. the addition is performed with the register carry from the 24th bit is ignored. the entire memory space can be addressed. this type of addressing is used for table data reads, etc. the a and b registers used in this addressing vary according to the value of the rss bit in the psw. when rss = 0, these registers are r1 and r3 respectively, and when rss = 1 they are r5 and r7. rss should only be set to 1 when using a 78k/iii series program. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format mem imm24[a], imm24[b], imm24[de], imm24[hl] mem1 imm24[a], imm24[b], imm24[de], imm24[hl] [description example] ? general example addc a, mem ? specific example addc a, 4010h[de] ; when indexed addressing using the sum of register de as mem and 04010h is selected [explanatory diagram] 23 effective address 0 memory 15/7 note 0 23 0 index address + register note 15 : when register is de or hl 7 : when register is a or b table+4 ? table+3 ? table+2 ? table+1 ? table ? ? table [a], when a = 3h : manipulation of a'th data item in table by table [a]
161 chapter 5 addressing 5.2.16 based indexed addressing [function] with this type of addressing, the register specified by the register specification code in the instruction word in the register bank specified by the register bank selection flag (rbs2, rbs1, rbs0) is used as the base register, and memory is addressed with the result of adding the value of a register specified in the same way to the contents of this base register as offset data. the addition is performed with the offset data extended to 24 bits as a positive number. a carry from the 24th bit is ignored. the entire memory space can be addressed. this type of addressing is used to specify in order data in an array in which one record consists of a number of bytes of data. the a, b, and c registers used in this addressing vary according to the value of the rss bit in the psw. when rss = 0, these registers are r1, r3, and r2 respectively, and when rss = 1 they are r5, r7, and r6. rss should only be set to 1 when using a 78k/iii series program. [operand format] performed when an instruction with one of the operand formats shown below is executed. identifier description format mem [tde + a], [tde + b], [tde + c], [whl + a], [whl + b], [whl + c], [vvp + de], [vvp + hl] mem1 [tde + a], [tde + b], [tde + c], [whl + a], [whl + b], [whl + c], [vvp + de], [vvp + hl] [description example] ? general example and a, mem ? specific example and a, [tde+b] ; when based addressing using the sum of register tde as mem and register b is selected record start address ? whl+c ? whl ? record start address ? whl + c manipulated with whl as record start address (when c = 2) one record of array : specific data in each record mov a, [whl+c]
162 chapter 5 addressing 23 effective address 0 memory 15/7 note 0 23 0 base register + offset register [explanatory diagram] note 15 : when register is de or hl 7 : when register is a, b or c
163 chapter 6 instruction set this chapter shows the 78k/iv series instruction set. 6.1 legend (1) operand identifiers and descriptions (1/2) identifier description format r, r note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7, r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r1 note 1 x(r0), a(r1), c(r2), b(r3), r4, r5, r6, r7 r2 r8, r9, r10, r11, e(r12), d(r13), l(r14), h(r15) r3 v, u, t, w rp, rp note 2 ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5), de(rp6), hl(rp7) rp1 note 2 ax(rp0), bc(rp1), rp2, rp3 rp2 vp(rp4), up(rp5), de(rp6), hl(rp7) rg, rg vvp(rg4), uup(rg5), tde(rg6), whl(rg7) sfr special function register symbol (see special function register application table ) sfrp special function register symbol (register for which 16-bit operation is possible: see special function register application table ) post note 2 multiple descriptions of ax(rp0), bc(rp1), rp2, rp3, vp(rp4), up(rp5)/psw, de(rp6) and hl(rp7) are permissible. however, up is only used with push/pop instructions, and psw with pushu/popu instructions. mem [tde], [whl], [tde +], [whl +], [tde C], [whl C], [vvp], [uup]: register indirect addressing [tde + byte], [whl + byte], [sp + byte], [uup + byte], [vvp + byte]: based addressing imm24[a], imm24[b], imm24[de], imm24[hl]: indexed addressing [tde + a], [tde + b], [tde + c], [whl + a], [whl + b], [whl + c], [vvp + de], [vvp + hl]: based indexed addressing mem1 all with [whl +], [whl C] excluded from mem mem2 [tde], [whl] mem3 [ax], [bc], [rp2], [rp3], [vvp], [uup], [tde], [whl] notes 1. setting the rss bit to 1 enables r4 to r7 to be used as x, a, c, and b, but this function should only be used when using a 78k/iii series program. 2. setting the rss bit to 1 enables rp2 and rp3 to be used as ax and bc, but this function should only be used when using a 78k/iii series program.
164 chapter 6 instruction set (1) operand identifiers and descriptions (2/2) identifier description format note saddr, saddr fd20h to ff1fh immediate data or label saddr1, saddr1 fe00h to feffh immediate data or label saddr2, saddr2 fd20h to fdffh, ff00h to ff1fh immediate data or label saddrp fd20h to ff1eh immediate data or label (16-bit operation) saddrp1 fe00h to fefeh immediate data or label (16-bit operation) saddrp2 fd20h to fdffh, ff00h to ff1eh immediate data or label (16-bit operation) saddrg fd20h to fefdh immediate data or label (24-bit operation) saddrg1 fe00h to fefdh immediate data or label (24-bit operation) saddrg2 fd20h to fdffh immediate data or label (24-bit operation) addr24 0h to ffffffh immediate data or label addr20 0h to fffffh immediate data or label addr16 0h to ffffh immediate data or label addr11 800h to fffh immediate data or label addr8 0fe00h to 0feffh note immediate data or label addr5 40h to 7eh immediate data or label imm24 24-bit immediate data or label word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label n 3-bit immediate data locaddr 00h or 0fh note the addresses shown here apply when 00h is specified by the location instruction. when 0fh is specified by the location instruction, f0000h should be added to the address values shown. the m pd784915 subseries is fixed to the location instruction.
165 chapter 6 instruction set (2) operand column symbols symbol description + auto-increment C auto-decrement # immediate data ! 16-bit absolute address !! 24-bit/20-bit absolute address $ 8-bit relative address $! 16-bit relative address / bit inversion [ ] indirect addressing [% ] 24-bit indirect addressing (3) flag column symbols symbol description (blank) no change 0 cleared to 0 1 set to 1 x set or cleared depending on result p p/v flag operates as parity flag v p/v flag operates as overflow flag r previously saved value is restored (4) operation field symbols symbol description jdisp8 signed twos complement data (8 bits) indicating relative address distance between start address of next instruction and branch address jdisp16 signed twos complement data (16 bits) indicating relative address distance between start address of next instruction and branch address pc hw pc bits 16 to 19 pc lw pc bits 0 to 15
166 chapter 6 instruction set (5) number of bytes of instruction that includes mem in operands mem mode register indirect addressing based indexed based indexed addressing addressing addressing number of bytes 1 2 note 352 note one-byte instruction only when [tde], [whl], [tde +], [tde C], [whl +], or [whl C] is written as mem in a mov instruction . (6) number of bytes of instruction that includes saddr, saddrp, r or rp in operands in some instructions which include saddr, saddrp, r, rp as operands, the number of bytes is written divided into two with /. which number of bytes is to be used depends on the table below. identifier number of bytes: left side number of bytes: right side saddr saddr2 saddr1 saddrp saddrp2 saddrp1 rr1 r2 rp rp1 rp2 (7) description of instructions that include mem in operands and string instructions operands tde, whl, vvp, and uup (24-bit registers) can also be written as de, hl, vp, and up respectively. however, they are still treated as tde, whl, vvp, and uup (24-bit registers) when written as de, hl, vp, and up.
167 chapter 6 instruction set 6.2 list of instruction operations (1) 8-bit data transfer instruction: mov mnemonic operands bytes operation flags s z ac p/v cy mov r, #byte 2/3 r byte saddr, #byte 3/4 (saddr) byte sfr, #byte 3 sfr byte !addr16, #byte 5 (addr16) byte !!addr24, #byte 6 (addr24) byte r, r 2/3 r r a, r 1/2 a r a, saddr2 2 a (saddr2) r, saddr 3 r (saddr) saddr2, a 2 (saddr2) a saddr, r 3 (saddr) r a, sfr 2 a sfr r, sfr 3 r sfr sfr, a 2 sfr a sfr, r 3 sfr r saddr, saddr 4 (saddr) (saddr) r, !addr16 4 r (addr16) !addr16, r 4 (addr16) r r, !!addr24 5 r (addr24) !!addr24, r 5 (addr24) r a, [saddrp] 2/3 a ((saddrp)) a, [%saddrg] 3/4 a ((saddrg)) a, mem 1-5 a (mem) [saddrp], a 2/3 ((saddrp)) a [%saddrg], a 3/4 ((saddrg)) a mem, a 1-5 (mem) a pswl, #byte 3 psw l byte pswh, #byte 3 psw h byte pswl, a 2 psw l a pswh, a 2 psw h a a, pswl 2 a psw l a, pswh 2 a psw h r3, #byte 3 r3 byte a, r3 2 a r3 r3, a 2 r3 a
168 chapter 6 instruction set (2) 16-bit data transfer instruction: movw mnemonic operands bytes operation flags s z ac p/v cy movw rp, #word 3 rp word saddrp, #word 4/5 (saddrp) word sfrp, #word 4 sfrp word !addr16, #word 6 (addr16) word !!addr24, #word 7 (addr24) word rp, rp 2 rp rp ax, saddrp2 2 ax (saddrp2) rp, saddrp 3 rp (saddrp) saddrp2, ax 2 (saddrp2) ax saddrp, rp 3 (saddrp) rp ax, sfrp 2 ax sfrp rp, sfrp 3 rp sfrp sfrp, ax 2 sfrp ax sfrp, rp 3 sfrp rp saddrp, saddrp 4 (saddrp) (saddrp) rp, !addr16 4 rp (addr16) !addr16, rp 4 (addr16) rp rp, !!addr24 5 rp (addr24) !!addr24, rp 5 (addr24) rp ax, [saddrp] 3/4 ax ((saddrp)) ax, [%saddrg] 3/4 ax ((saddrg)) ax, mem 2-5 ax (mem) [saddrp], ax 3/4 ((saddrp)) ax [%saddrg], ax 3/4 ((saddrg)) ax mem, ax 2-5 (mem) ax
169 chapter 6 instruction set (3) 24-bit data transfer instruction: movg mnemonic operands bytes operation flags s z ac p/v cy movg rg, #imm24 5 rg imm24 rg, rg 2 rg rg rg, !!addr24 5 rg (addr24) !!addr24, rg 5 (addr24) rg rg, saddrg 3 rg (saddrg) saddrg, rg 3 (saddrg) rg whl, [%saddrg] 3/4 whl ((saddrg)) [%saddrg], whl 3/4 ((saddrg)) whl whl, mem1 2-5 whl (mem1) mem1, whl 2-5 (mem1) whl (4) 8-bit data exchange instruction: xch mnemonic operands bytes operation flags s z ac p/v cy xch r, r 2/3 r r a, r 1/2 a r a, saddr2 2 a (saddr2) r, saddr 3 r (saddr) r, sfr 3 r sfr saddr, saddr 4 (saddr) (saddr) r, !addr16 4 r (addr16) r, !!addr24 5 r (addr24) a, [saddrp] 2/3 a ((saddrp)) a, [%saddrg] 3/4 a ((saddrg)) a, mem 2-5 a (mem)
170 chapter 6 instruction set (5) 16-bit data exchange instruction: xchw mnemonic operands bytes operation flags s z ac p/v cy xchw rp, rp 2 rp rp ax, saddrp2 2 ax (saddrp2) rp, saddrp 3 rp (saddrp) rp, sfrp 3 rp sfrp ax, [saddrp] 3/4 ax ((saddrp)) ax, [%saddrg] 3/4 ax ((saddrg)) ax, !addr16 4 ax (addr16) ax, !!addr24 5 ax (addr24) saddrp, saddrp 4 (saddrp) (saddrp) ax, mem 2-5 ax (mem) (6) 8-bit operation instructions: add, addc, sub, subc, cmp, and, or, xor mnemonic operands bytes operation flags s z ac p/v cy add a, #byte 2 a, cy a + byte v r, #byte 3 r, cy r + byte v saddr, #byte 3/4 (saddr), cy (saddr) + byte v sfr, #byte 4 sfr, cy sfr + byte v r, r 2/3 r, cy r + r v a, saddr2 2 a, cy a + (saddr2) v r, saddr 3 r, cy r + (saddr) v saddr, r 3 (saddr), cy (saddr) + r v r, sfr 3 r, cy r + sfr v sfr, r 3 sfr, cy sfr + r v saddr, saddr 4 (saddr), cy (saddr) + (saddr) v a, [saddrp] 3/4 a, cy a + ((saddrp)) v a, [%saddrg] 3/4 a, cy a + ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a v a, !addr16 4 a, cy a + (addr16) v a, !!addr24 5 a, cy a + (addr24) v !addr16, a 4 (addr16), cy (addr16) + a v !!addr24, a 5 (addr24), cy (addr24) + a v a, mem 2-5 a, cy a + (mem) v mem, a 2-5 (mem), cy (mem) + a v
171 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy addc a, #byte 2 a, cy a + byte + cy v r, #byte 3 r, cy r + byte + cy v saddr, #byte 3/4 (saddr), cy (saddr) + byte + cy v sfr, #byte 4 sfr, cy sfr + byte + cy v r, r 2/3 r, cy r + r + cy v a, saddr2 2 a, cy a + (saddr2) + cy v r, saddr 3 r, cy r + (saddr) + cy v saddr, r 3 (saddr), cy (saddr) + r + cy v r, sfr 3 r, cy r + sfr + cy v sfr, r 3 sfr, cy sfr + r + cy v saddr, saddr 4 (saddr), cy (saddr) + (saddr) + cy v a, [saddrp] 3/4 a, cy a + ((saddrp)) + cy v a, [%saddrg] 3/4 a, cy a + ((saddrg)) + cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) + a + cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) + a + cy v a, !addr16 4 a, cy a + (addr16) + cy v a, !!addr24 5 a, cy a + (addr24) + cy v !addr16, a 4 (addr16), cy (addr16) + a + cy v !!addr24, a 5 (addr24), cy (addr24) + a + cy v a, mem 2-5 a, cy a + (mem) + cy v mem, a 2-5 (mem), cy (mem) + a + cy v
172 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy sub a, #byte 2 a, cy a C byte v r, #byte 3 r, cy r C byte v saddr, #byte 3/4 (saddr), cy (saddr) C byte v sfr, #byte 4 sfr, cy sfr C byte v r, r 2/3 r, cy r C r v a, saddr2 2 a, cy a C (saddr2) v r, saddr 3 r, cy r C (saddr) v saddr, r 3 (saddr), cy (saddr) C r v r, sfr 3 r, cy r C sfr v sfr, r 3 sfr, cy sfr C r v saddr, saddr 4 (saddr), cy (saddr) C (saddr) v a, [saddrp] 3/4 a, cy a C ((saddrp)) v a, [%saddrg] 3/4 a, cy a C ((saddrg)) v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) C a v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) C a v a, !addr16 4 a, cy a C (addr16) v a, !!addr24 5 a, cy a C (addr24) v !addr16, a 4 (addr16), cy (addr16) C a v !!addr24, a 5 (addr24), cy (addr24) C a v a, mem 2-5 a, cy a C (mem) v mem, a 2-5 (mem), cy (mem) C a v
173 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy subc a, #byte 2 a, cy a C byte C cy v r, #byte 3 r, cy r C byte C cy v saddr, #byte 3/4 (saddr), cy (saddr) C byte C cy v sfr, #byte 4 sfr, cy sfr C byte C cy v r, r 2/3 r, cy r C r C cy v a, saddr2 2 a, cy a C (saddr2) C cy v r, saddr 3 r, cy r C (saddr) C cy v saddr, r 3 (saddr), cy (saddr) C r C cy v r, sfr 3 r, cy r C sfr C cy v sfr, r 3 sfr, cy sfr C r C cy v saddr, saddr 4 (saddr), cy (saddr) C (saddr) C cy v a, [saddrp] 3/4 a, cy a C ((saddrp)) C cy v a, [%saddrg] 3/4 a, cy a C ((saddrg)) C cy v [saddrp], a 3/4 ((saddrp)), cy ((saddrp)) C a C cy v [%saddrg], a 3/4 ((saddrg)), cy ((saddrg)) C a C cy v a, !addr16 4 a, cy a C (addr16) C cy v a, !!addr24 5 a, cy a C (addr24) C cy v !addr16, a 4 (addr16), cy (addr16) C a C cy v !!addr24, a 5 (addr24), cy (addr24) C a C cy v a, mem 2-5 a, cy a C (mem) C cy v mem, a 2-5 (mem), cy (mem) C a C cy v
174 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy cmp a, #byte 2 a C byte v r, #byte 3 r C byte v saddr, #byte 3/4 (saddr) C byte v sfr, #byte 4 sfr C byte v r, r 2/3 r C r v a, saddr2 2 a C (saddr2) v r, saddr 3 r C (saddr) v saddr, r 3 (saddr) C r v r, sfr 3 r C sfr v sfr, r 3 sfr C r v saddr, saddr 4 (saddr) C (saddr) v a, [saddrp] 3/4 a C ((saddrp)) v a, [%saddrg] 3/4 a C ((saddrg)) v [saddrp], a 3/4 ((saddrp)) C a v [%saddrg], a 3/4 ((saddrg)) C a v a, !addr16 4 a C (addr16) v a, !!addr24 5 a C (addr24) v !addr16, a 4 (addr16) C a v !!addr24, a 5 (addr24) C a v a, mem 2-5 a C (mem) v mem, a 2-5 (mem) C a v
175 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy and a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr) p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p
176 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy or a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr) p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (saddr16) p a, !!addr24 5 a a (saddr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p
177 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy xor a, #byte 2 a a byte p r, #byte 3 r r byte p saddr, #byte 3/4 (saddr) (saddr) byte p sfr, #byte 4 sfr sfr byte p r, r 2/3 r r r p a, saddr2 2 a a (saddr2) p r, saddr 3 r r (saddr) p saddr, r 3 (saddr) (saddr) r p r, sfr 3 r r sfr p sfr, r 3 sfr sfr r p saddr, saddr 4 (saddr) (saddr) (saddr) p a, [saddrp] 3/4 a a ((saddrp)) p a, [%saddrg] 3/4 a a ((saddrg)) p [saddrp], a 3/4 ((saddrp)) ((saddrp)) a p [%saddrg], a 3/4 ((saddrg)) ((saddrg)) a p a, !addr16 4 a a (addr16) p a, !!addr24 5 a a (addr24) p !addr16, a 4 (addr16) (addr16) a p !!addr24, a 5 (addr24) (addr24) a p a, mem 2-5 a a (mem) p mem, a 2-5 (mem) (mem) a p
178 chapter 6 instruction set (7) 16-bit operation instructions: addw, subw, cmpw mnemonic operands bytes operation flags s z ac p/v cy addw ax, #word 3 ax, cy ax + word v rp, #word 4 rp, cy rp + word v rp, rp 2 rp, cy rp + rp v ax, saddrp2 2 ax, cy ax + (saddrp2) v rp, saddrp 3 rp, cy rp + (saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) + rp v rp, sfrp 3 rp, cy rp + sfrp v sfrp, rp 3 sfrp, cy sfrp + rp v saddrp, #word 4/5 (saddrp), cy (saddrp) + word v sfrp, #word 5 sfrp, cy sfrp + word v saddrp, saddrp 4 (saddrp), cy (saddrp) + (saddrp) v subw ax, #word 3 ax, cy ax C word v rp, #word 4 rp, cy rp C word v rp, rp 2 rp, cy rp C rp v ax, saddrp2 2 ax, cy ax C (saddrp2) v rp, saddrp 3 rp, cy rp C (saddrp) v saddrp, rp 3 (saddrp), cy (saddrp) C rp v rp, sfrp 3 rp, cy rp C sfrp v sfrp, rp 3 sfrp, cy sfrp C rp v saddrp, #word 4/5 (saddrp), cy (saddrp) C word v sfrp, #word 5 sfrp, cy sfrp C word v saddrp, saddrp 4 (saddrp), cy (saddrp) C (saddrp) v cmpw ax, #word 3 ax C word v rp, #word 4 rp C word v rp, rp 2 rp C rp v ax, saddrp2 2 ax C (saddrp2) v rp, saddrp 3 rp C (saddrp) v saddrp, rp 3 (saddrp) C rp v rp, sfrp 3 rp C sfrp v sfrp, rp 3 sfrp C rp v saddrp, #word 4/5 (saddrp) C word v sfrp, #word 5 sfrp C word v saddrp, saddrp 4 (saddrp) C (saddrp) v
179 chapter 6 instruction set (8) 24-bit operation instructions: addg, subg mnemonic operands bytes operation flags s z ac p/v cy addg rg, rg 2 rg, cy rg + rg v rg, #imm24 5 rg, cy rg + imm24 v whl, saddrg 3 whl, cy whl + (saddrg) v subg rg, rg 2 rg, cy rg C rg v rg, #imm24 5 rg, cy rg C imm24 v whl, saddrg 3 whl, cy whl C (saddrg) v (9) multiplication instructions: mulu, muluw, mulw, divuw, divux mnemonic operands bytes operation flags s z ac p/v cy mulu r 2/3 ax a r muluw rp 2 ax (higher half), rp (lower half) ax rp mulw rp 2 ax (higher half), rp (lower half) ax rp divuw r 2/3 ax (quotient), r (remainder) ax r note 1 divux rp 2 axde (quotient), rp (remainder) axde rp note 2 notes 1. when r = 0, r x, ax ffffh 2. when rp = 0, rp de, axde ffffffffh (10) special operation instructions: macw, macsw, sacw mnemonic operands bytes operation flags s z ac p/v cy macw byte 3 axde (b) (c) + axde, b b + 2, v c c + 2, byte byte C 1 end if (byte = 0 or p/v = 1) macsw byte 3 axde (b) (c) + axde, b b + 2, v c c + 2, byte byte C 1 if byte = 0 then end if p/v = 1 then if overflow axde 7fffffffh, end if underflow axde 80000000h, end sacw [tde +], [whl +] 4 ax | (tde) C (whl) | + ax, v tde tde + 2, whl whl + 2 c c C 1 end if (c = 0 or cy = 1)
180 chapter 6 instruction set (11) increment/decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operands bytes operation flags s z ac p/v cy inc r 1/2 r r + 1 v saddr 2/3 (saddr) (saddr) + 1 v dec r 1/2 r r C 1 v saddr 2/3 (saddr) (saddr) C 1 v incw rp 2/1 rp rp + 1 saddrp 3/4 (saddrp) (saddrp) + 1 decw rp 2/1 rp rp C 1 saddrp 3/4 (saddrp) (saddrp) C 1 incg rg 2 rg rg + 1 decg rg 2 rg rg C 1 (12) adjustment instructions: adjba, adjbs, cvtbw mnemonic operands bytes operation flags s z ac p/v cy adjba 2 decimal adjust accumulator after addition p adjbs 2 decimal adjust accumulator after subtract p cvtbw 1x a, a 00h if a 7 = 0 x a, a ffh if a 7 = 1
181 chapter 6 instruction set (13) shift/rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operands bytes operation flags s z ac p/v cy ror r, n 2/3 (cy, r 7 r 0 , r m C 1 r m ) x n n = 0 C 7 p rol r, n 2/3 (cy, r 0 r 7 , r m + 1 r m ) x n n = 0 C 7 p rorc r, n 2/3 (cy r 0 , r 7 cy, r m C 1 r m ) x n n = 0 C 7 p rolc r, n 2/3 (cy r 7 , r 0 cy, r m + 1 r m ) x n n = 0 C 7 p shr r, n 2/3 (cy r 0 , r 7 0, r m C 1 r m ) x n n = 0 C 7 0p shl r, n 2/3 (cy r 7 , r 0 0, r m + 1 r m ) x n n = 0 C 7 0p shrw rp, n 2 (cy rp 0 , rp 15 0, rp m C 1 rp m ) x n 0p n = 0 C 7 shlw rp, n 2 (cy rp 15 , rp 0 0, rp m + 1 rp m ) x n 0p n = 0 C 7 ror4 mem3 2 a 3 C 0 (mem3) 3 C 0 , (mem3) 7 C 4 a 3 C 0 , (mem3) 3 C 0 (mem3) 7 C 4 rol4 mem3 2 a 3 C 0 (mem3) 7 C 4 , (mem3) 3 C 0 a 3 C 0 , (mem3) 7 C 4 (mem3) 3 C 0
182 chapter 6 instruction set (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 mnemonic operands bytes operation flags s z ac p/v cy mov1 cy, saddr.bit 3/4 cy (saddr.bit) cy, sfr.bit 3 cy sfr.bit cy, x.bit 2 cy x.bit cy, a.bit 2 cy a.bit cy, pswl.bit 2 cy psw l .bit cy, pswh.bit 2 cy psw h .bit cy, !addr16.bit 5 cy !addr16.bit cy, !!addr24.bit 6 cy !!addr24.bit cy, mem2.bit 2 cy mem2.bit saddr.bit, cy 3/4 (saddr.bit) cy sfr.bit, cy 3 sfr.bit cy x.bit, cy 2 x.bit cy a.bit, cy 2 a.bit, cy pswl.bit, cy 2 psw l .bit cy pswh.bit, cy 2 psw h .bit cy !addr16.bit, cy 5 !addr16.bit cy !!addr24.bit, cy 6 !!addr24.bit cy mem2.bit, cy 2 mem2.bit cy and1 cy, saddr.bit 3/4 cy cy (saddr.bit) cy, /saddr.bit 3/4 cy cy (saddr.bit) cy, sfr.bit 3 cy cy sfr.bit cy, /sfr.bit 3 cy cy sfr.bit cy, x.bit 2 cy cy x.bit cy, /x.bit 2 cy cy x.bit cy, a.bit 2 cy cy a.bit cy, /a.bit 2 cy cy a.bit cy, pswl.bit 2 cy cy psw l .bit cy, /pswl.bit 2 cy cy psw l .bit cy, pswh.bit 2 cy cy psw h .bit cy, /pswh.bit 2 cy cy psw h .bit cy, !addr16.bit 5 cy cy !addr16.bit cy, /!addr16.bit 5 cy cy !addr16.bit cy, !!addr24.bit 6 cy cy !!addr24.bit cy, /!!addr24.bit 6 cy cy !!addr24.bit cy, mem2.bit 2 cy cy mem2.bit cy, /mem2.bit 2 cy cy mem2.bit
183 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy or1 cy, saddr.bit 3/4 cy cy (saddr.bit) cy, /saddr.bit 3/4 cy cy (saddr.bit) cy, sfr.bit 3 cy cy sfr.bit cy, /sfr.bit 3 cy cy sfr.bit cy, x.bit 2 cy cy x.bit cy, /x.bit 2 cy cy x.bit cy, a.bit 2 cy cy a.bit cy, /a.bit 2 cy cy a.bit cy, pswl.bit 2 cy cy psw l .bit cy, /pswl.bit 2 cy cy psw l .bit cy, pswh.bit 2 cy cy psw h .bit cy, /pswh.bit 2 cy cy psw h .bit cy, !addr16.bit 5 cy cy !addr16.bit cy, /!addr16.bit 5 cy cy !addr16.bit cy, !!addr24.bit 6 cy cy !!addr24.bit cy, /!!addr24.bit 6 cy cy !!addr24.bit cy, mem2.bit 2 cy cy mem2.bit cy, /mem2.bit 2 cy cy mem2.bit xor1 cy, saddr.bit 3/4 cy cy (saddr.bit) cy, sfr.bit 3 cy cy sfr.bit cy, x.bit 2 cy cy x.bit cy, a.bit 2 cy cy a.bit cy, pswl.bit 2 cy cy psw l .bit cy, pswh.bit 2 cy cy psw h .bit cy, !addr16.bit 5 cy cy !addr16.bit cy, !!addr24.bit 6 cy cy !!addr24.bit cy, mem2.bit 2 cy cy mem2.bit not1 saddr.bit 3/4 (saddr.bit) (saddr.bit) sfr.bit 3 sfr.bit sfr.bit x.bit 2 x.bit x.bit a.bit 2 a.bit a.bit pswl.bit 2 pswl.bit psw l .bit pswh.bit 2 pswh.bit psw h .bit !addr16.bit 5 !addr16.bit !addr16.bit !!addr24.bit 6 !!addr24.bit !!addr24.bit mem2.bit 2 mem2.bit mem2.bit cy 1 cy cy
184 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy set1 saddr.bit 2/3 (saddr.bit) 1 sfr.bit 3 sfr.bit 1 x.bit 2 x.bit 1 a.bit 2 a.bit 1 pswl.bit 2 psw l .bit 1 pswh.bit 2 psw h .bit 1 !addr16.bit 5 !addr16.bit 1 !!addr24.bit 6 !!addr24.bit 1 mem2.bit 2 mem2.bit 1 cy 1 cy 11 clr1 saddr.bit 2/3 (saddr.bit) 0 sfr.bit 3 sfr.bit 0 x.bit 2 x.bit 0 a.bit 2 a.bit 0 pswl.bit 2 psw l .bit 0 pswh.bit 2 psw h .bit 0 !addr16.bit 5 !addr16.bit 0 !!addr24.bit 6 !!addr24.bit 0 mem2.bit 2 mem2.bit 0 cy 1 cy 00
185 chapter 6 instruction set (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operands bytes operation flags s z ac p/v cy push note 1 psw 1 (sp C 2) psw, sp sp C 2 sfrp 3 (sp C 2) sfrp, sp sp C 2 sfr 3 (sp C 1) sfr, sp sp C 1 post 2 {(sp C 2) post, sp sp C 2} m note 2 rg 2 (sp C 3) rg, sp sp C 3 pushu note 1 post 2 {(uup C 2) post, uup uup C 2} m note 2 pop note 1 psw 1 psw (sp), sp sp + 2 rrrrr sfrp 3 sfrp (sp), sp sp + 2 sfr 3 sfr (sp), sp sp + 1 post 2 {post (sp), sp sp + 2} m note 2 rg 2 rg (sp), sp sp + 3 popu note 1 post 2 {post (uup), uup uup + 2} m note 2 movg sp, #imm24 5 sp imm24 sp, whl 2 sp whl whl, sp 2 whl sp addwg sp, #word 4 sp sp + word subwg sp, #word 4 sp sp C word incg sp 2 sp sp + 1 decg sp 2 sp sp C 1 notes 1. for details about operation, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. 2. m = number of registers specified by post
186 chapter 6 instruction set (16) call/return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operands bytes operation flags s z ac p/v cy call note !addr16 3 (sp C 3) (pc + 3), sp sp C 3, pc hw 0, pc lw addr16 !!addr20 4 (sp C 3) (pc + 4), sp sp C 3, pc addr20 rp 2 (sp C 3) (pc + 2), sp sp C 3, pc hw 0, pc lw rp rg 2 (sp C 3) (pc + 2), sp sp C 3, pc rg [rp] 2 (sp C 3) (pc + 2), sp sp C 3, pc hw 0, pc lw (rp) [rg] 2 (sp C 3) (pc + 2), sp sp C 3, pc (rg) $!addr20 3 (sp C 3) (pc + 3), sp sp C 3, pc pc + 3 + jdisp16 callf note !addr11 2 (sp C 3) (pc + 2), sp sp C 3 pc 19 C 12 0, pc 11 1, pc 10 C 0 addr11 callt note [addr5] 1 (sp C 3) (pc + 1), sp sp C 3, pc hw 0, pc lw (addr5) brk 1 (sp C 2) psw, (sp C 1) 0 C 3 (pc + 1) hw , (sp C 4) pc + 1, sp sp C 4 pc hw 0, pc lw (003eh) brkcs rbn 2 pc lw rp2, rp3 psw, rbs2 C 0 n, rss 0, ie 0, rp3 8 C 11 pc hw , pc hw 0 ret note 1 pc (sp), sp sp + 3 reti note 1 pc (sp), psw (sp + 2), sp sp + 4 rrrrr retb note 1 pc (sp), psw (sp + 2), sp sp + 4 rrrrr retcs !addr16 3 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8 C 11 retcsb !addr16 4 psw rp3, pc lw rp2, rp2 addr16, rrrrr pc hw rp3 8 C 11 note for details about operation, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3- 5 data restored from stack area.
187 chapter 6 instruction set (17) unconditional branch instruction: br mnemonic operands bytes operation flags s z ac p/v cy br !addr16 3 pc hw 0, pc lw addr16 !!addr20 4 pc addr20 rp 2 pc hw 0, pc lw rp rg 2 pc rg [rp] 2 pc hw 0, pc lw (rp) [rg] 2 pc (rg) $addr20 2 pc pc + 2 + jdisp8 $!addr20 3 pc pc + 3 + jdisp16
188 chapter 6 instruction set (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz mnemonic operands bytes operation flags s z ac p/v cy bnz $addr20 2 pc pc + 2 + jdisp8 if z = 0 bne bz $addr20 2 pc pc + 2 + jdisp8 if z = 1 be bnc $addr20 2 pc pc + 2 + jdisp8 if cy = 0 bnl bc $addr20 2 pc pc + 2 + jdisp8 if cy = 1 bl bnv $addr20 2 pc pc + 2 + jdisp8 if p/v = 0 bpo bv $addr20 2 pc pc + 2 + jdisp8 if p/v = 1 bpe bp $addr20 2 pc pc + 2 + jdisp8 if s = 0 bn $addr20 2 pc pc + 2 + jdisp8 if s = 1 blt $addr20 3 pc pc + 3 + jdisp8 if p/v s = 1 bge $addr20 3 pc pc + 3 + jdisp8 if p/v s = 0 ble $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 1 bgt $addr20 3 pc pc + 3 + jdisp8 if (p/v s) z = 0 bnh $addr20 3 pc pc + 3 + jdisp8 if z cy = 1 bh $addr20 3 pc pc + 3 + jdisp8 if z cy = 0 bf saddr.bit, $addr20 4/5 pc pc + 4 note + jdisp8 if(saddr.bit) = 0 sfr.bit, $addr20 4 pc pc + 4 + jdisp8 if sfr.bit = 0 x.bit, $addr20 3 pc pc + 3 + jdisp8 if x.bit = 0 a.bit, $addr20 3 pc pc + 3 + jdisp8 if a.bit = 0 pswl.bit, $addr20 3 pc pc + 3 + jdisp8 if psw l .bit = 0 pswh.bit, $addr20 3 pc pc + 3 + jdisp8 if psw h .bit = 0 !addr16.bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16.bit = 0 !!addr24.bit, $addr20 7 pc pc + 3 + jdisp8 if !!addr24.bit = 0 mem2.bit, $addr20 3 pc pc + 3 + jdisp8 if mem2.bit = 0 note when the number of bytes is 4; when 5, the operation is: pc pc + 5 + jdisp8.
189 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy bt saddr.bit, $addr20 3/4 pc pc + 3 note 1 + jdisp8 if(saddr.bit) = 1 sfr.bit, $addr20 4 pc pc + 4 + jdisp8 if sfr.bit = 1 x.bit, $addr20 3 pc pc + 3 + jdisp8 if x.bit = 1 a.bit, $addr20 3 pc pc + 3 + jdisp8 if a.bit = 1 pswl.bit, $addr20 3 pc pc + 3 + jdisp8 if psw l .bit = 1 pswh.bit, $addr20 3 pc pc + 3 + jdisp8 if psw h .bit = 1 !addr16.bit, $addr20 6 pc pc + 3 + jdisp8 if !addr16.bit = 1 !!addr24.bit, $addr20 7 pc pc + 3 + jdisp8 if !!addr24.bit = 1 mem2.bit, $addr20 3 pc pc + 3 + jdisp8 if mem2.bit = 1 btclr saddr.bit, $addr20 4/5 {pc pc + 4 note 2 + jdisp8, (saddr.bit) 0} if(saddr.bit) = 1 sfr.bit, $addr20 4 {pc pc + 4 + jdisp8, sfr.bit 0} if sfr.bit = 1 x.bit, $addr20 3 {pc pc + 3 + jdisp8, x.bit 0} if x.bit = 1 a.bit, $addr20 3 {pc pc + 3 + jdisp8, a.bit 0} if a.bit = 1 pswl.bit, $addr20 3 {pc pc + 3 + jdisp8, psw l .bit 0} if psw l .bit = 1 pswh.bit, $addr20 3 {pc pc + 3 + jdisp8, psw h .bit 0} if psw h .bit = 1 !addr16.bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16.bit 0} if !addr16 = 1 !!addr24.bit, $addr20 7 {pc pc + 3 + jdisp8, !!addr24.bit 0} if !!addr24 = 1 mem2.bit, $addr20 3 {pc pc + 3 + jdisp8, mem2.bit 0} if mem2. bit = 1 notes 1. when the number of bytes is 3; when 4, the operation is: pc pc + 4 + jdisp8. 2. when the number of bytes is 4; when 5, the operation is: pc pc + 5 + jdisp8.
190 chapter 6 instruction set mnemonic operands bytes operation flags s z ac p/v cy bfset saddr.bit, $addr20 4/5 {pc pc + 4 note 1 + jdisp8, (saddr.bit) 1} if(saddr.bit) = 0 sfr.bit, $addr20 4 {pc pc + 4 + jdisp8, sfr.bit 1} if sfr.bit = 0 x.bit, $addr20 3 {pc pc + 3 + jdisp8, x.bit 1} if x.bit = 0 a.bit, $addr20 3 {pc pc + 3 + jdisp8, a.bit 1} if a.bit = 0 pswl.bit, $addr20 3 {pc pc + 3 + jdisp8, psw l .bit 1} if psw l .bit = 0 pswh.bit, $addr20 3 {pc pc + 3 + jdisp8, psw h .bit 1} if psw h .bit = 0 !addr16.bit, $addr20 6 {pc pc + 3 + jdisp8, !addr16.bit 1} if !addr16 = 0 !!addr24.bit, $addr20 7 {pc pc + 3 + jdisp8, !!addr24.bit 1} if !!addr24 = 0 mem2.bit, $addr20 3 {pc pc + 3 + jdisp8, mem2.bit 1} if mem2.bit = 0 dbnz b, $addr20 2 b b C 1, pc pc + 2 + jdisp8 if b 0 c, $addr20 2 c c C 1, pc pc + 2 + jdisp8 if c 0 saddr, $addr20 3/4 (saddr) (saddr) C 1, pc pc + 3 note 2 + jdisp8 if (saddr) 0 notes 1. when the number of bytes is 4; when 5, the operation is: pc pc + 5 + jdisp8. 2. when the number of bytes is 3; when 4, the operation is: pc pc + 4 + jdisp8.
191 chapter 6 instruction set (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operands bytes operation flags s z ac p/v cy mov stbc, #byte 4 stbc byte wdm, #byte 4 wdm byte location locaddr 4 sfr, internal data area location address high-order word specification sel rbn 2 rss 0, rbs2 C 0 n rbn, alt 2 rss 1, rbs2 C 0 n swrs 2 rss rss nop 1 no operation ei 1 ie 1(enable interrupt) di 1 ie 0(disable interrupt) (20) special instructions: chkl, chkla mnemonic operands bytes operation flags s z ac p/v cy chkl sfr 3 (pin level) (output latch) p chkla sfr 3 a (pin level) (output latch) p caution the chkl and chkla instructions are not available in the m pd784216, 784216y, 784218, 784218y, 784225, 784225y, 784937 subseries. do not execute these instructions. if these instructions are executed, the following operations will result. ? chkl instruction ....... after the pin levels of the output pins are read two times, they are exclusive-ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1). ? chkla instruction .... after the pin levels of output pins are read two times, they are exclusive- ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1) along with that the result is stored in the a register.
192 chapter 6 instruction set (21) string instructions: movtblw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, cmpbknc mnemonic operands bytes operation flags s z ac p/v cy movtblw !addr8, byte 4 (addr8 + 2) (addr8), byte byte C 1, addr8 addr8 C 2 end if byte = 0 movm [tde +], a 2 (tde) a, tde tde + 1, c c C 1 end if c = 0 [tde C], a 2 (tde) a, tde tde C 1, c c C 1 end if c = 0 xchm [tde +], a 2 (tde) a, tde tde + 1, c c C 1 end if c = 0 [tde C], a 2 (tde) a, tde tde C 1, c c C 1 end if c = 0 movbk [tde +], [whl +] 2 (tde) (whl), tde tde + 1, whl whl + 1, c c C 1 end if c = 0 [tde C], [whl C] 2 (tde) (whl), tde tde C 1, whl whl C 1, c c C 1 end if c = 0 xchbk [tde +], [whl +] 2 (tde) (whl), tde tde + 1, whl whl + 1, c c C 1 end if c = 0 [tde C], [whl C] 2 (tde) (whl), tde tde C 1, whl whl C 1, c c C 1 end if c = 0 cmpme [tde +], a 2 (tde) C a, tde tde + 1, c c C 1 end if c = 0 or z = 0 v [tde C], a 2 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or z = 0 v cmpmne [tde +], a 2 (tde) C a, tde tde + 1, c c C 1 end if c = 0 or z = 1 v [tde C], a 2 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or z = 1 v cmpmc [tde +], a 2 (tde) C a, tde tde + 1, c c C 1 end if c = 0 or cy = 0 v [tde C], a 2 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or cy = 0 v cmpmnc [tde +], a 2 (tde) C a, tde tde + 1, c c C 1 end if c = 0 or cy = 1 v [tde C], a 2 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or cy = 1 v cmpbke [tde +], [whl +] 2 (tde) C (whl), tde tde + 1, v whl whl + 1, c c C 1 end if c = 0 or z = 0 [tde C], [whl C] 2 (tde) C (whl), tde tde C 1, v whl whl C 1, c c C 1 end if c = 0 or z = 0 cmpbkne [tde +], [whl +] 2 (tde) C (whl), tde tde + 1, v whl whl + 1, c c C 1 end if c = 0 or z = 1 [tde C], [whl C] 2 (tde) C (whl), tde tde C 1, v whl whl C 1, c c C 1 end if c = 0 or z = 1 cmpbkc [tde +], [whl +] 2 (tde) C (whl), tde tde + 1, v whl whl + 1, c c C 1 end if c = 0 or cy = 0 [tde C], [whl C] 2 (tde) C (whl), tde tde C 1, v whl whl C 1, c c C 1 end if c = 0 or cy = 0 cmpbknc [tde +], [whl +] 2 (tde) C (whl), tde tde + 1, v whl whl + 1, c c C 1 end if c = 0 or cy = 1 [tde C], [whl C] 2 (tde) C (whl), tde tde C 1, v whl whl C 1, c c C 1 end if c = 0 or cy = 1
193 chapter 6 instruction set 6.3 instructions listed by type of addressing (1) 8-bit instructions (combinations expressed by writing a for r are shown in parentheses) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 6-1. list of instructions by 8-bit addressing 2nd operand #byte a r saddr sfr !addr16 mem r3 [whl +] n no note 2 r saddr !!addr24 [saddrp] pswl [whl C] 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde +] (mov) movbk note 5 [tde C] (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are equivalent to add. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. rol, rorc, rolc, shr, and shl are equivalent to ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are equivalent to movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are equvalent to movbk. 6. when saddr is saddr2 in this combination, a short code length instruction can be used.
194 chapter 6 instruction set (2) 16-bit instructions (combinations expressed by writing ax for rp are shown in parentheses) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 6-2. list of instructions by 16-bit addressing 2nd operand #word ax rp saddrp sfrp !addr16 mem [whl +] byte n no note 2 rp saddrp !!addr24 [saddrp] 1st operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) notes 1, 3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde +] (movw) sacw byte macw macsw notes 1. subw and cmpw are equivalent to addw. 2. there is no 2nd operand, or the 2nd operand is not an operand address. 3. when saddrp is saddrp2 in this combination, a short code length instruction can be used. 4. muluw and divux are equivalent to mulw.
195 chapter 6 instruction set (3) 24-bit instructions (combinations expressed by writing whl for rg are shown in parentheses) movg, addg, subg, incg, decg, push, pop table 6-3. list of instructions by 24-bit addressing 2nd #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp no note operand rg 1st operand whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note there is no 2nd operand, or the 2nd operand is not an operand address.
196 chapter 6 instruction set (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 6-4. list of instructions by bit manipulation instruction addressing 2nd operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit no note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit !addr16.bit /!addr16.bit 1st operand !!addr24.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh. bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note there is no 2nd operand, or the 2nd operand is not an operand address.
197 chapter 6 instruction set (5) call/return instructions/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 6-5. list of instructions by call/return instruction/branch instruction addressing instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn no address operand basic instructions bc note call call call call call call call callf callt brkcs brk br br br br br br br br ret retcs reti retcsb retb compound bf instructions bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are equivalent to bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs
198 chapter 6 instruction set 6.4 operation codes 6.4.1 operation code symbols (1) r1 (2) r2 r 2 r 1 r 0 r1 r 2 r 1 r 0 r2 000 r0 000 r8 001 r1 001 r9 010 r2 010 r10 011 r3 011 r11 100 r4 100 r12 101 r5 101 r13 110 r6 110 r14 111 r7 111 r15 (3) r, r (4) rp r 3 r 2 r 1 r 0 rp 7 p 6 p 5 rp r 7 r 6 r 5 r 4 r 0000 r0 000 rp0 0001 r1 001 rp1 0010 r2 010 rp2 0011 r3 011 rp3 0100 r4 100 rp4 0101 r5 101 rp5 0110 r6 110 rp6 0111 r7 111 rp7 1000 r8 1001 r9 1010 r10 1011 r11 1100 r12 1101 r13 1110 r14 1111 r15
199 chapter 6 instruction set (5) rp, rp (6) rg, rg p 2 p 1 p 0 rp g 6 g 5 rg rp g 2 g 1 rg 000 rp0 00 rg4 001 rp4 01 rg5 010 rp1 10 rg6 011 rp5 11 rg7 100 rp2 101 rp6 110 rp3 111 rp7 (7) mem3 p 2 p 1 p 0 mem3 0 0 0 [rp0] 0 0 1 [rg4] 0 1 0 [rp1] 0 1 1 [rg5] 1 0 0 [rp2] 1 0 1 [rg6] 1 1 0 [rp3] 1 1 1 [rg7]
200 chapter 6 instruction set (8) post byte note up in the case of a push/pop instruction, psw in the case of a pushu/popu instruction. (9) locaddr locaddr locaddrl locaddrh 0 feh 01h 0fh ffh 00h 0 1 save/restore operation not performed on stack memory save/restore operation performed on stack memory ax bc rp2 rp3 vp up/psw note de hl bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding register pair
201 chapter 6 instruction set 6.4.2 list of operation codes (1) 8-bit data transfer instruction: mov mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mov r1, #byte 1 0 1 1 1 r 2 r 1 r 0 ? #byte ? r2, #byte 0 0 1 1 1 1 0 0 1 0 1 1 1 r 2 r 1 r 0 ? #byte ? saddr2, #byte 0 0 1 1 1 0 1 0 ? saddr2-offset ?? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 0 ? saddr1-offset ? ? #byte ? sfr, #byte 0 0 1 0 1 0 1 1 ? sfr-offset ?? #byte ? !addr16, #byte 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 ? low address ? ? high address ?? #byte ? !!addr24, #byte 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 0 ? high-w address ? ? low address ?? high address ?? #byte ? r, r1 0010 0100 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 0010 0100 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, r1 1 1 0 1 0 r 2 r 1 r 0 a, r2 0011 1100 1101 0r 2 r 1 r 0 a, saddr2 0 0 1 0 0 0 0 0 ? saddr2-offset ? r, saddr2 0 0 1 1 1 0 0 0 r 3 r 2 r 1 r 0 0000 ? saddr2-offset ? r, saddr1 0 0 1 1 1 0 0 0 r 3 r 2 r 1 r 0 0001 ? saddr1-offset ? saddr2, a 0 0 1 0 0 0 1 0 ? saddr2-offset ? saddr2, r 0 0 1 1 1 0 0 0 r 3 r 2 r 1 r 0 0100 ? saddr2-offset ? saddr1, r 0 0 1 1 1 0 0 0 r 3 r 2 r 1 r 0 0101 ? saddr1-offset ? a, sfr 0 0 0 1 0 0 0 0 ? sfr-offset ? r, sfr 0 0 1 1 1 0 0 0 r 3 r 2 r 1 r 0 0010 ? sfr-offset ? sfr, a 0 0 0 1 0 0 1 0 ? sfr-offset ? sfr, r 0 0 1 1 1 0 0 0 r 3 r 2 r 1 r 0 0110 ? sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 ? saddr2-offset ? ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 0 ? saddr1-offset ? ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 0 ? saddr2-offset ? ? saddr1-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
202 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mov saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 0 0 0 0 ? saddr1-offset ? ? saddr1-offset ? r, !addr16 0 0 1 1 1 1 1 0 r 3 r 2 r 1 r 0 0000 ? low address ? ? high address ? !addr16, r 0 0 1 1 1 1 1 0 r 3 r 2 r 1 r 0 0001 ? low address ? ? high address ? r, !!addr24 0 0 1 1 1 1 1 0 r 3 r 2 r 1 r 0 0010 ? high-w address ? ? low address ?? high address ? !!addr24, r 0 0 1 1 1 1 1 0 r 3 r 2 r 1 r 0 0011 ? high-w address ? ? low address ?? high address ? a, [saddrp2] 0 0 0 1 1 0 0 0 ? saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 ? saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 ? saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 ? saddr1-offset ? a, [tde +] 0 1 0 1 1 0 0 0 a, [whl +] 0 1 0 1 1 0 0 1 a, [tde C] 0 1 0 1 1 0 1 0 a, [whl C] 0 1 0 1 1 0 1 1 a, [tde] 0 1 0 1 1 1 0 0 a, [whl] 0 1 0 1 1 1 0 1 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 0 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 0 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 ? low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 ? low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 ? low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 0 ? low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 ? low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
203 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mov a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 0 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 0 a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 0 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 0 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 0 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 0 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 [saddrp2], a 0 0 0 1 1 0 0 1 ? saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 ? saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 0 ? saddr2-offset ? [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 0 ? saddr1-offset ? [tde +], a 0 1 0 1 0 0 0 0 [whl +], a 0 1 0 1 0 0 0 1 [tde C], a 0 1 0 1 0 0 1 0 [whl C], a 0 1 0 1 0 0 1 1 [tde], a 0 1 0 1 0 1 0 0 [whl], a 0 1 0 1 0 1 0 1 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 0 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 ? low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 ? low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 ? low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 ? low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 ? low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
204 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mov imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 0 ? low offset ? ? high offset ?? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 0 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 0 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 0 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 0 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 0 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 pswl, #byte 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 0 ? #byte ? pswh, #byte 0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 ? #byte ? pswl, a 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 0 pswh, a 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 a, pswl 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 a, pswh 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 v, #byte 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 1 ? #byte ? u, #byte 0 0 0 0 0 1 1 1 0 1 1 0 0 0 1 1 ? #byte ? t, #byte 0 0 0 0 0 1 1 1 0 1 1 0 0 1 0 1 ? #byte ? w, #byte 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 1 ? #byte ? a, v 0000 0101 1100 0001 a, u 0000 0101 1100 0011 a, t 0000 0101 1100 0101 a, w 0000 0101 1100 0111 v, a 0000 0101 1100 1001 u, a 0000 0101 1100 1011 t, a 0000 0101 1100 1101 w, a 0000 0101 1100 1111 --------------------------------------------------------------------------------
205 chapter 6 instruction set (2) 16-bit data transfer instruction: movw mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movw rp, #word 0 1 1 0 0 p 2 p 1 p 0 ? low byte ?? high byte ? saddrp2, #word 0 0 0 0 1 1 0 0 ? saddr2-offset ?? low byte ? ? high byte ? saddrp1, #word 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 ? saddr1-offset ? ? low byte ?? high byte ? sfrp, #word 0 0 0 0 1 0 1 1 ? sfr-offset ?? low byte ? ? high byte ? !addr16, #word 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 ? low address ? ? high address ?? low byte ?? high byte ? !!addr24, #word 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1 ? high-w address ? ? low address ?? high address ?? low byte ? ? high byte ? rp, rp 0 0 1 0 0 1 0 0 p 7 p 6 p 5 01p 2 p 1 p 0 ax, saddrp2 0 0 0 1 1 1 0 0 ? saddr2-offset ? rp, saddrp2 0 0 1 1 1 0 0 0 p 7 p 6 p 5 0 1000 ? saddr2-offset ? rp, saddrp1 0 0 1 1 1 0 0 0 p 7 p 6 p 5 0 1001 ? saddr1-offset ? saddrp2, ax 0 0 0 1 1 0 1 0 ? saddr2-offset ? saddrp2, rp 0 0 1 1 1 0 0 0 p 7 p 6 p 5 0 1100 ? saddr2-offset ? saddrp1, rp 0 0 1 1 1 0 0 0 p 7 p 6 p 5 0 1101 ? saddr1-offset ? ax, sfrp 0 0 0 1 0 0 0 1 ? sfr-offset ? rp, sfrp 0 0 1 1 1 0 0 0 p 7 p 6 p 5 0 1010 ? sfr-offset ? sfrp, ax 0 0 0 1 0 0 1 1 ? sfr-offset ? sfrp, rp 0 0 1 1 1 0 0 0 p 7 p 6 p 5 0 1110 ? sfr-offset ? saddrp2, saddrp2 0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 ? saddr2-offset ? ? saddr2-offset ? saddrp2, saddrp1 0 0 1 0 1 0 1 0 1 0 0 1 0 0 0 0 ? saddr1-offset ? ? saddr2-offset ? saddrp1, saddrp2 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 ? saddr2-offset ? ? saddr1-offset ? saddrp1, saddrp1 0 0 1 0 1 0 1 0 1 0 1 1 0 0 0 0 ? saddr1-offset ? ? saddr1-offset ? rp, !addr16 0 0 1 1 1 1 1 0 p 7 p 6 p 5 0 1000 ? low address ? ? high address ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
206 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movw !addr16, rp 0 0 1 1 1 1 1 0 p 7 p 6 p 5 0 1001 ? low address ? ? high address ? rp, !!addr24 0 0 1 1 1 1 1 0 p 7 p 6 p 5 0 1010 ? high-w address ? ? low address ?? high address ? !!addr24, rp 0 0 1 1 1 1 1 0 p 7 p 6 p 5 0 1011 ? high-w address ? ? low address ?? high address ? ax, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 ? saddr2-offset ? ax, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 0 0 1 ? saddr1-offset ? ax, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 ? saddr2-offset ? ax, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 ? saddr1-offset ? ax, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 1 ax, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 0 0 0 1 ax, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 1 ax, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1 ax, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 ax, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 0 0 0 1 ax, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 0 0 0 1 ax, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 ax, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 ? low offset ? ax, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 1 ? low offset ? ax, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 ? low offset ? ax, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 ? low offset ? ax, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 1 ? low offset ? ax, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 1 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
207 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movw ax, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 0 0 0 1 ax, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 0 0 0 1 ax, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 0 0 0 1 ax, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 0 0 0 1 ax, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 0 0 0 1 ax, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 0 0 0 1 ax, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0 1 [saddrp2], ax 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 ? saddr2-offset ? [saddrp1], ax 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 1 ? saddr1-offset ? [%saddrg2], ax 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 ? saddr2-offset ? [%saddrg1], ax 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 0 1 ? saddr1-offset ? [tde +], ax 0 0 0 1 0 1 1 0 1 0 0 0 0 0 0 1 [whl +], ax 0 0 0 1 0 1 1 0 1 0 0 1 0 0 0 1 [tde C], ax 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 [whlC], ax 0 0 0 1 0 1 1 0 1 0 1 1 0 0 0 1 [tde], ax 0 0 0 1 0 1 1 0 1 1 0 0 0 0 0 1 [whl], ax 0 0 0 1 0 1 1 0 1 1 0 1 0 0 0 1 [vvp], ax 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 1 [uup], ax 0 0 0 1 0 1 1 0 1 1 1 1 0 0 0 1 [tde + byte], ax 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 ? low offset ? [sp + byte], ax 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 ? low offset ? [whl + byte], ax 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 1 ? low offset ? [uup + byte], ax 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 1 ? low offset ? [vvp + byte], ax 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 ? low offset ? imm24 [de], ax 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], ax 0 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], ax 0 0 0 0 1 0 1 0 1 0 1 0 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [b], ax 0 0 0 0 1 0 1 0 1 0 1 1 0 0 0 1 ? low offset ? ? high offset ?? high-w offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
208 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movw [tde + a], ax 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 1 [whl + a], ax 0 0 0 1 0 1 1 1 1 0 0 1 0 0 0 1 [tde + b], ax 0 0 0 1 0 1 1 1 1 0 1 0 0 0 0 1 [whl + b], ax 0 0 0 1 0 1 1 1 1 0 1 1 0 0 0 1 [vvp + de], ax 0 0 0 1 0 1 1 1 1 1 0 0 0 0 0 1 [vvp + hl], ax 0 0 0 1 0 1 1 1 1 1 0 1 0 0 0 1 [tde + c], ax 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 [whl + c], ax 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 1
209 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- (3) 24-bit data transfer instruction: movg mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movg rg, #imm24 0 0 1 1 1 0 0 0 1 g 6 g 5 1 1011 ? low byte ? ? high byte ?? high-w byte ? rg, rg 0 0 1 0 0 1 0 0 1 g 6 g 5 11g 2 g 1 1 rg, !!addr24 0 0 1 1 1 1 1 0 1 g 6 g 5 1 1010 ? high-w address ? ? low address ?? high address ? !!addr24, rg 0 0 1 1 1 1 1 0 1 g 6 g 5 1 1011 ? high-w address ? ? low address ?? high address ? rg, saddrg2 0 0 1 1 1 0 0 0 1 g 6 g 5 1 1000 ? saddr2-offset ? rg, saddrg1 0 0 1 1 1 0 0 0 1 g 6 g 5 1 1001 ? saddr1-offset ? saddrg2, rg 0 0 1 1 1 0 0 0 1 g 6 g 5 1 1100 ? saddr2-offset ? saddrg1, rg 0 0 1 1 1 0 0 0 1 g 6 g 5 1 1101 ? saddr1-offset ? whl, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 ? saddr2-offset ? whl, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 ? saddr1-offset ? [%saddrg2], whl 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 ? saddr2-offset ? [%saddrg1], whl 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 0 ? saddr1-offset ? whl, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 whl, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 0 0 1 0 whl, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 0 whl, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 0 0 1 0 whl, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 0 0 1 0 whl, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 0 0 1 0 whl, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 ? low offset ? whl, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 ? low offset ? whl, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 ? low offset ? whl, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 0 ? low offset ? whl, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 ? low offset ? whl, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? whl, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? (continued on next page)
210 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movg whl, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? whl, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? whl, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 0 0 1 0 whl, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 0 0 1 0 whl, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 0 0 1 0 whl, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 0 0 1 0 whl, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 whl, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 0 0 1 0 whl, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 whl, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 0 0 1 0 [tde +], whl 0 0 0 1 0 1 1 0 1 0 0 0 0 0 1 0 [tde C], whl 0 0 0 1 0 1 1 0 1 0 1 0 0 0 1 0 [tde], whl 0 0 0 1 0 1 1 0 1 1 0 0 0 0 1 0 [whl], whl 0 0 0 1 0 1 1 0 1 1 0 1 0 0 1 0 [vvp], whl 0 0 0 1 0 1 1 0 1 1 1 0 0 0 1 0 [uup], whl 0 0 0 1 0 1 1 0 1 1 1 1 0 0 1 0 [tde + byte], whl 0 0 0 0 0 1 1 0 1 0 0 0 0 0 1 0 ? low offset ? [sp + byte], whl 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 ? low offset ? [whl + byte], whl 0 0 0 0 0 1 1 0 1 0 1 0 0 0 1 0 ? low offset ? [uup + byte], whl 0 0 0 0 0 1 1 0 1 0 1 1 0 0 1 0 ? low offset ? [vvp + byte], whl 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 ? low offset ? imm24 [de], whl 0 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], whl 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], whl 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [b], whl 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 0 ? low offset ? ? high offset ?? high-w offset ? [tde + a], whl 0 0 0 1 0 1 1 1 1 0 0 0 0 0 1 0 [whl + a], whl 0 0 0 1 0 1 1 1 1 0 0 1 0 0 1 0 [tde + b], whl 0 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
211 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movg [whl + b], whl 0 0 0 1 0 1 1 1 1 0 1 1 0 0 1 0 [vvp + de], whl 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0 [vvp + hl], whl 0 0 0 1 0 1 1 1 1 1 0 1 0 0 1 0 [tde + c], whl 0 0 0 1 0 1 1 1 1 1 1 0 0 0 1 0 [whl + c], whl 0 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0
212 chapter 6 instruction set (4) 8-bit data exchange instruction: xch mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xch r, r1 0010 0101 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 0010 0101 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, r1 1 1 0 1 1 r 2 r 1 0 a, r2 0011 1100 1101 1r 2 r 1 r 0 a, saddr2 0 0 1 0 0 0 0 1 ? saddr2-offset ? r, saddr2 0 0 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0000 ? saddr2-offset ? r, saddr1 0 0 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0001 ? saddr1-offset ? r, sfr 0 0 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0010 ? sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 0 1 0 0 ? saddr2-offset ? ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 0 1 0 0 ? saddr1-offset ? ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 ? saddr2-offset ? ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 0 1 0 0 ? saddr1-offset ? ? saddr1-offset ? r, !addr16 0 0 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0100 ? low address ? ? high address ? r, !!addr24 0 0 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0110 ? high-w address ? ? low address ?? high address ? a, [saddrp2] 0 0 1 0 0 0 1 1 ? saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 1 0 0 0 1 1 ? saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 ? saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 ? saddr1-offset ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 0 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 0 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 0 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 0 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 0 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 0 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
213 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xch a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 ? low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 0 ? low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 ? low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 0 ? low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 0 ? low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 ? low offset ? ? high offset ?? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 0 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 0 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 0 1 0 0 a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0 0 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 0 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 0 1 0 0 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 0 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 0 1 0 0 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
214 chapter 6 instruction set (5) 16-bit data exchange instruction: xchw mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xchw rp, rp 0 0 1 0 0 1 0 1 p 7 p 6 p 5 01p 2 p 1 p 0 ax, saddrp2 0 0 0 1 1 0 1 1 ? saddr2-offset ? rp, saddrp2 0 0 1 1 1 0 0 1 p 7 p 6 p 5 0 1000 ? saddr2-offset ? rp, saddrp1 0 0 1 1 1 0 0 1 p 7 p 6 p 5 0 1001 ? saddr1-offset ? rp, sfrp 0 0 1 1 1 0 0 1 p 7 p 6 p 5 0 1010 ? sfr-offset ? ax, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 ? saddr2-offset ? ax, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 0 1 0 1 ? saddr1-offset ? ax, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 ? saddr2-offset ? ax, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 ? saddr1-offset ? ax, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 0 1 0 1 ? low address ? ? high address ? ax, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 1 ? high-w address ? ? low address ?? high address ? saddrp2, saddrp2 0 0 1 0 1 0 1 0 1 0 0 0 0 1 0 0 ? saddr2-offset ? ? saddr2-offset ? saddrp2, saddrp1 0 0 1 0 1 0 1 0 1 0 0 1 0 1 0 0 ? saddr1-offset ? ? saddr2-offset ? saddrp1, saddrp2 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 ? saddr2-offset ? ? saddr1-offset ? saddrp1, saddrp1 0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 0 ? saddr1-offset ? ? saddr1-offset ? ax, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 ? low offset ? ax, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 ? low offset ? ax, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 1 ? low offset ? ax, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 0 1 0 1 ? low offset ? ax, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 0 1 0 1 ? low offset ? ax, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 ? low offset ? ? high offset ?? high-w offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
215 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xchw ax, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 0 1 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 0 1 0 1 ? low offset ? ? high offset ?? high-w offset ? ax, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 0 1 0 1 ax, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 0 1 0 1 ax, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 0 1 0 1 ax, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 ax, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 ax, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 0 1 0 1 ax, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 0 1 0 1 ax, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 ax, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 0 1 0 1 ax, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 0 1 0 1 ax, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 0 1 0 1 ax, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 0 1 0 1 ax, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 ax, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 0 1 0 1 ax, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 0 1 0 1 ax, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
216 chapter 6 instruction set (6) 8-bit operation instructions: add, addc, sub, subc, cmp, and, or, xor mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 add a, #byte 1 0 1 0 1 0 0 0 ? #byte ? r, #byte 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0011 ? #byte ? saddr2, #byte 0 1 1 0 1 0 0 0 ? saddr2-offset ?? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 0 ? saddr1-offset ? ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 ? sfr-offset ? ? #byte ? r, r1 1000 1000 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1000 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 0 0 0 ? saddr2-offset ? r, saddr2 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0000 ? saddr2-offset ? r, saddr1 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0001 ? saddr1-offset ? saddr2, r 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0100 ? saddr2-offset ? saddr1, r 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0101 ? saddr1-offset ? r, sfr 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0010 ? sfr-offset ? sfr, r 0 1 1 1 1 0 0 0 r 7 r 6 r 5 r 4 0110 ? sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 ? saddr2-offset ? ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 0 ? saddr1-offset ? ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 0 ? saddr2-offset ? ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 0 0 0 ? saddr1-offset ? ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 ? saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 0 ? saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 ? saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 0 ? saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 ? saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 0 ? saddr1-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
217 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 add [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 ? saddr2-offset ? [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 0 ? saddr1 offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 0 ? low address ? ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 0 ? high-w address ? ? low address ?? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 0 ? low address ? ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 0 0 0 ? high-w address ? ? low address ?? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 0 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 0 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 0 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 0 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 0 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 0 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 ? low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 ? low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 ? low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 0 ? low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 0 ? low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 0 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
218 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 add a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 0 a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 0 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 0 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 0 0 0 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 0 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 0 0 0 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 0 0 0 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 0 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 0 0 0 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 0 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 0 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 0 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 0 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 0 0 0 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 ? low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 ? low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 0 ? low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 ? low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 ? low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 0 ? low offset ? ? high offset ?? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 0 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 0 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 0 0 0 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 0 0 0 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 0 0 0 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 0 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 0 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
219 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 addc a, #byte 1 0 1 0 1 0 0 1 ? #byte ? r, #byte 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0011 ? #byte ? saddr2, #byte 0 1 1 0 1 0 0 1 ? saddr2-offset ?? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 ? saddr1-offset ? ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 1 ? sfr-offset ? ? #byte ? r, r1 1000 1001 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1001 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 0 0 1 ? saddr2-offset ? r, saddr2 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0000 ? saddr2-offset ? r, saddr1 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0001 ? saddr1-offset ? saddr2, r 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0100 ? saddr2-offset ? saddr1, r 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0101 ? saddr1-offset ? r, sfr 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0010 ? sfr-offset ? sfr, r 0 1 1 1 1 0 0 1 r 7 r 6 r 5 r 4 0110 ? sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 1 ? saddr2-offset ? ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 ? saddr1-offset ? ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 ? saddr2-offset ? ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 0 0 1 ? saddr1-offset ? ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 ? saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 0 1 ? saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 ? saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 0 1 ? saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 ? saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 ? saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 ? saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
220 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 addc [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 0 1 ? saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 0 0 1 ? low address ? ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 ? high-w address ? ? low address ?? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 0 0 1 ? low address ? ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 ? high-w address ? ? low address ?? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 0 0 1 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 1 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 0 0 1 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 0 0 1 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 0 0 1 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1 ? low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 1 ? low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 ? low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 ? low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 ? low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 0 0 1 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 0 0 1 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 0 0 1 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
221 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 addc a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 0 0 1 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 1 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 0 0 1 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 0 0 1 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 0 0 1 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 0 0 1 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 0 0 1 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 1 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 0 0 1 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 0 0 1 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 0 0 1 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 0 0 1 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 ? low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 ? low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 0 0 1 ? low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 1 ? low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 1 ? low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 0 0 1 ? low offset ? ? high offset ?? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 0 0 1 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 1 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 0 0 1 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 0 0 1 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 0 0 1 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 0 0 1 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 1 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 0 0 1 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
222 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 sub a, #byte 1 0 1 0 1 0 1 0 ? #byte ? r, #byte 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0011 ? #byte ? saddr2, #byte 0 1 1 0 1 0 1 0 ? saddr2 offset ?? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 0 1 0 ? saddr1-offset ? ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 ? sfr-offset ? ? #byte ? r, r1 1000 1010 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1010 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 0 1 0 ? saddr2-offset ? r, saddr2 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0000 ? saddr2-offset ? r, saddr1 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0001 ? saddr1-offset ? saddr2, r 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0100 ? saddr2-offset ? saddr1, r 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0101 ? saddr1-offset ? r, sfr 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0010 ? sfr-offset ? sfr, r 0 1 1 1 1 0 1 0 r 7 r 6 r 5 r 4 0110 ? sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 0 ? saddr2-offset ? ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 0 ? saddr1-offset ? ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 0 ? saddr2-offset ? ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 0 ? saddr1-offset ? ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 ? saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 0 ? saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 ? saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 0 ? saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 ? saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 ? saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 0 ? saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
223 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 sub [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 0 ? saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 0 ? low address ? ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 0 ? high-w address ? ? low address ?? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 ? low address ? ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 0 1 0 ? high-w address ? ? low address ?? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 0 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 0 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 0 1 0 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 0 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 0 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 0 ? low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 0 ? low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 ? low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 0 ? low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 0 ? low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 0 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 0 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 0 1 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
224 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 sub a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 0 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 0 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 0 1 0 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 0 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 0 1 0 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 0 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1 0 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 0 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 0 1 0 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 0 1 0 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 0 ? low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 0 ? low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 ? low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 0 ? low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 ? low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0 ? low offset ? ? high offset ?? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 0 1 0 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 0 1 0 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 0 1 0 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 0 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 0 1 0 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 0 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 0 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
225 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 subc a, #byte 1 0 1 0 1 0 1 1 ? #byte ? r, #byte 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0011 ? #byte ? saddr2, #byte 0 1 1 0 1 0 1 1 ? saddr2-offset ?? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 0 1 1 ? saddr1-offset ? ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 ? sfr-offset ? ? #byte ? r, r1 1000 1011 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1011 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 0 1 1 ? saddr2-offset ? r, saddr2 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0000 ? saddr2-offset ? r, saddr1 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0001 ? saddr1-offset ? saddr2, r 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0100 ? saddr2-offset ? saddr1, r 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0101 ? saddr1-offset ? r, sfr 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0010 ? sfr-offset ? sfr, r 0 1 1 1 1 0 1 1 r 7 r 6 r 5 r 4 0110 ? sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 ? saddr2-offset ? ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 0 1 1 ? saddr1-offset ? ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 1 ? saddr2-offset ? ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 ? saddr1-offset ? ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 ? saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 ? saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 1 ? saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 0 1 1 ? saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 1 ? saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 1 ? saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 ? saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
226 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 subc [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 0 1 1 ? saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 0 1 1 ? low address ? ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 0 1 1 ? high-w address ? ? low address ?? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 0 1 1 ? low address ? ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 0 1 1 ? high-w address ? ? low address ?? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 0 1 1 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 0 1 1 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 0 1 1 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 1 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 0 1 1 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 0 1 1 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 0 1 1 ? low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 1 ? low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 ? low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 0 1 1 ? low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1 1 ? low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 0 1 1 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 0 1 1 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 0 1 1 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
227 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 subc a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 0 1 1 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 1 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 1 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 0 1 1 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 0 1 1 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 0 1 1 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 0 1 1 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 0 1 1 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 0 1 1 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 0 1 1 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 0 1 1 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 0 1 1 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 0 1 1 ? low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 ? low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 ? low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1 ? low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 0 1 1 ? low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1 ? low offset ? ? high offset ?? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 0 1 1 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 0 1 1 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 1 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 0 1 1 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 0 1 1 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 0 1 1 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 0 1 1 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 0 1 1 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
228 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 cmp a, #byte 1 0 1 0 1 1 1 1 #byte ? r, #byte 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0011 #byte ? saddr2, #byte 0 1 1 0 1 1 1 1 saddr2-offset ? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 1 saddr1-offset ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 1 sfr-offset ? #byte ? r, r1 1000 1111 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1111 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 1 1 1 saddr2-offset ? r, saddr2 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0000 saddr2-offset ? r, saddr1 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0001 saddr1-offset ? saddr2, r 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0100 saddr2-offset ? saddr1, r 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0101 saddr1-offset ? r, sfr 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0010 sfr-offset ? sfr, r 0 1 1 1 1 1 1 1 r 7 r 6 r 5 r 4 0110 sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 saddr2-offset ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1 saddr1-offset ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 1 saddr2-offset ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 1 saddr1-offset ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 1 saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 1 saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 1 saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 1 saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 1 saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
229 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 cmp [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 1 saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 1 low address ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 1 high-w address ? low address ? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 low address ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 high-w address ? low address ? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 1 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 1 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 1 1 1 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 1 1 1 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 1 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1 1 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 1 low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 1 low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 1 low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 1 low offset ? high offset ? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 1 low offset ? high offset ? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 1 low offset ? high offset ? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 1 low offset ? high offset ? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 1 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 1 1 1 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 1 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
230 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 cmp a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 1 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 1 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 1 1 1 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 1 1 1 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 1 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 1 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 1 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 1 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 1 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 1 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 1 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 1 1 1 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 1 low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 1 low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 1 low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 1 low offset ? high offset ? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 low offset ? high offset ? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 1 low offset ? high offset ? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 low offset ? high offset ? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 1 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 1 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 1 1 1 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 1 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 1 1 1 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 1 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
231 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 and a, #byte 1 0 1 0 1 1 0 0 #byte ? r, #byte 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0011 #byte ? saddr2, #byte 0 1 1 0 1 1 0 0 saddr2-offset ? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 0 saddr1-offset ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 0 sfr-offset ? #byte ? r, r1 1000 1100 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1100 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 1 0 0 saddr2-offset ? r, saddr2 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0000 saddr2-offset ? r, saddr1 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0001 saddr1-offset ? saddr2, r 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0100 saddr2-offset ? saddr1, r 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0101 saddr1-offset ? r, sfr 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0010 sfr-offset ? sfr, r 0 1 1 1 1 1 0 0 r 7 r 6 r 5 r 4 0110 sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 0 saddr2-offset ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 0 saddr1-offset ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 0 saddr2-offset ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 0 saddr1-offset ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 0 saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
232 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 and [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 0 low address ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 0 high-w address ? low address ? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 0 low address ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 1 0 0 high-w address ? low address ? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 0 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 0 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 1 0 0 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 1 0 0 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 0 low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 0 low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 low offset ? high offset ? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 0 low offset ? high offset ? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 low offset ? high offset ? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 0 low offset ? high offset ? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 1 0 0 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
233 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 and a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 1 0 0 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 0 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 0 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 0 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 1 0 0 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 1 0 0 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 0 low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 0 low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 0 low offset ? high offset ? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 0 low offset ? high offset ? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 0 low offset ? high offset ? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 0 low offset ? high offset ? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 0 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 0 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 0 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 0 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 1 0 0 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 0 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 1 0 0 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
234 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 or a, #byte 1 0 1 0 1 1 1 0 #byte ? r, #byte 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0011 #byte ? saddr2, #byte 0 1 1 0 1 1 1 0 saddr2-offset ? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 1 1 0 saddr1-offset ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 1 1 0 sfr-offset ? #byte ? r, r1 1000 1110 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1110 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 1 1 0 saddr2-offset ? r, saddr2 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0000 saddr2-offset ? r, saddr1 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0001 saddr1-offset ? saddr2, r 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0100 saddr2-offset ? saddr1, r 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0101 saddr1-offset ? r, sfr 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0010 sfr-offset ? sfr, r 0 1 1 1 1 1 1 0 r 7 r 6 r 5 r 4 0110 sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 0 saddr2-offset ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 saddr1-offset ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 saddr2-offset ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 1 0 saddr1-offset ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 1 0 saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 0 saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
235 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 or [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 1 0 saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 1 1 0 low address ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 1 1 0 high-w address ? low address ? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0 low address ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 0 high-w address ? low address ? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 1 1 0 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 0 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 1 1 0 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 1 1 0 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 1 1 0 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 1 1 0 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 1 1 0 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 1 1 0 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 1 1 0 low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 1 1 0 low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 1 1 0 low offset ? high offset ? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 1 1 0 low offset ? high offset ? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 1 1 0 low offset ? high offset ? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 low offset ? high offset ? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 0 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 1 1 0 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 1 1 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
236 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 or a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 1 1 0 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 1 1 0 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 1 1 0 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 1 1 0 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 1 1 0 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 1 1 0 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 1 1 0 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 1 1 0 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 1 1 0 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 1 1 0 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 0 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 0 low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 1 1 0 low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 0 low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 1 1 0 low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 1 1 0 low offset ? high offset ? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 0 low offset ? high offset ? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 1 1 0 low offset ? high offset ? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 0 low offset ? high offset ? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 1 1 0 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 0 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 1 1 0 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 0 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 1 1 0 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 1 1 0 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 0 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 0 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
237 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xor a, #byte 1 0 1 0 1 1 0 1 #byte ? r, #byte 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0011 #byte ? saddr2, #byte 0 1 1 0 1 1 0 1 saddr2-offset ? #byte ? saddr1, #byte 0 0 1 1 1 1 0 0 0 1 1 0 1 1 0 1 saddr1-offset ? #byte ? sfr, #byte 0 0 0 0 0 0 0 1 0 1 1 0 1 1 0 1 sfr-offset ? #byte ? r, r1 1000 1101 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 r, r2 0011 1100 1000 1101 r 7 r 6 r 5 r 4 0r 2 r 1 r 0 a, saddr2 1 0 0 1 1 1 0 1 saddr2-offset ? r, saddr2 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0000 saddr2-offset ? r, saddr1 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0001 saddr1-offset ? saddr2, r 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0100 saddr2-offset ? saddr1, r 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0101 saddr1-offset ? r, sfr 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0010 sfr-offset ? sfr, r 0 1 1 1 1 1 0 1 r 7 r 6 r 5 r 4 0110 sfr-offset ? saddr2, saddr2 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 1 saddr2-offset ? saddr2-offset ? saddr2, saddr1 0 0 1 0 1 0 1 0 0 0 0 1 1 1 0 1 saddr1-offset ? saddr2-offset ? saddr1, saddr2 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 1 saddr2-offset ? saddr1-offset ? saddr1, saddr1 0 0 1 0 1 0 1 0 0 0 1 1 1 1 0 1 saddr1-offset ? saddr1-offset ? a, [saddrp2] 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 saddr2-offset ? a, [saddrp1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 saddr1-offset ? a, [%saddrg2] 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 1 saddr2-offset ? a, [%saddrg1] 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 0 1 saddr1-offset ? [saddrp2], a 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 saddr2-offset ? [saddrp1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 1 saddr1-offset ? [%saddrg2], a 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
238 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xor [%saddrg1], a 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 1 1 0 1 saddr1-offset ? a, !addr16 0 0 0 0 1 0 1 0 0 1 0 0 1 1 0 1 low address ? high address ? a, !!addr24 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 1 high-w address ? low address ? high address ? !addr16, a 0 0 0 0 1 0 1 0 1 1 0 0 1 1 0 1 low address ? high address ? !!addr24, a 0 0 0 0 1 0 1 0 1 1 0 1 1 1 0 1 high-w address ? low address ? high address ? a, [tde +] 0 0 0 1 0 1 1 0 0 0 0 0 1 1 0 1 a, [whl +] 0 0 0 1 0 1 1 0 0 0 0 1 1 1 0 1 a, [tde C] 0 0 0 1 0 1 1 0 0 0 1 0 1 1 0 1 a, [whl C] 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 1 a, [tde] 0 0 0 1 0 1 1 0 0 1 0 0 1 1 0 1 a, [whl] 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 1 a, [vvp] 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 1 a, [uup] 0 0 0 1 0 1 1 0 0 1 1 1 1 1 0 1 a, [tde + byte] 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 low offset ? a, [sp + byte] 0 0 0 0 0 1 1 0 0 0 0 1 1 1 0 1 low offset ? a, [whl + byte] 0 0 0 0 0 1 1 0 0 0 1 0 1 1 0 1 low offset ? a, [uup + byte] 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 1 low offset ? a, [vvp + byte] 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 1 low offset ? a, imm24 [de] 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 1 low offset ? high offset ? high-w offset ? a, imm24 [a] 0 0 0 0 1 0 1 0 0 0 0 1 1 1 0 1 low offset ? high offset ? high-w offset ? a, imm24 [hl] 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1 low offset ? high offset ? high-w offset ? a, imm24 [b] 0 0 0 0 1 0 1 0 0 0 1 1 1 1 0 1 low offset ? high offset ? high-w offset ? a, [tde + a] 0 0 0 1 0 1 1 1 0 0 0 0 1 1 0 1 a, [whl + a] 0 0 0 1 0 1 1 1 0 0 0 1 1 1 0 1 a, [tde + b] 0 0 0 1 0 1 1 1 0 0 1 0 1 1 0 1 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
239 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 xor a, [whl + b] 0 0 0 1 0 1 1 1 0 0 1 1 1 1 0 1 a, [vvp + de] 0 0 0 1 0 1 1 1 0 1 0 0 1 1 0 1 a, [vvp + hl] 0 0 0 1 0 1 1 1 0 1 0 1 1 1 0 1 a, [tde + c] 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 1 a, [whl + c] 0 0 0 1 0 1 1 1 0 1 1 1 1 1 0 1 [tde +], a 0 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 [whl +], a 0 0 0 1 0 1 1 0 1 0 0 1 1 1 0 1 [tde C], a 0 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 [whl C], a 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 [tde], a 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 1 [whl], a 0 0 0 1 0 1 1 0 1 1 0 1 1 1 0 1 [vvp], a 0 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 [uup], a 0 0 0 1 0 1 1 0 1 1 1 1 1 1 0 1 [tde + byte], a 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 low offset ? [sp + byte], a 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 low offset ? [whl + byte], a 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 low offset ? [uup + byte], a 0 0 0 0 0 1 1 0 1 0 1 1 1 1 0 1 low offset ? [vvp + byte], a 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 low offset ? imm24 [de], a 0 0 0 0 1 0 1 0 1 0 0 0 1 1 0 1 low offset ? high offset ? high-w offset ? imm24 [a], a 0 0 0 0 1 0 1 0 1 0 0 1 1 1 0 1 low offset ? high offset ? high-w offset ? imm24 [hl], a 0 0 0 0 1 0 1 0 1 0 1 0 1 1 0 1 low offset ? high offset ? high-w offset ? imm24 [b], a 0 0 0 0 1 0 1 0 1 0 1 1 1 1 0 1 low offset ? high offset ? high-w offset ? [tde + a], a 0 0 0 1 0 1 1 1 1 0 0 0 1 1 0 1 [whl + a], a 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 1 [tde + b], a 0 0 0 1 0 1 1 1 1 0 1 0 1 1 0 1 [whl + b], a 0 0 0 1 0 1 1 1 1 0 1 1 1 1 0 1 [vvp + de], a 0 0 0 1 0 1 1 1 1 1 0 0 1 1 0 1 [vvp + hl], a 0 0 0 1 0 1 1 1 1 1 0 1 1 1 0 1 [tde + c], a 0 0 0 1 0 1 1 1 1 1 1 0 1 1 0 1 [whl + c], a 0 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
240 chapter 6 instruction set (7) 16-bit operation instructions: addw, subw, cmpw mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 addw ax, #word 0 0 1 0 1 1 0 1 low byte ? high byte ? rp, #word 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1011 low byte ? high byte ? rp, rp 1 0 0 0 1 0 0 0 p 7 p 6 p 5 01p 2 p 1 p 0 ax, saddrp2 0 0 0 1 1 1 0 1 saddr2-offset ? rp, saddrp2 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1000 saddr2-offset ? rp, saddrp1 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1001 saddr1-offset ? saddrp2, rp 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1100 saddr2-offset ? saddrp1, rp 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1101 saddr1-offset ? rp, sfrp 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1010 sfr-offset ? sfrp, rp 0 1 1 1 1 0 0 0 p 7 p 6 p 5 0 1110 sfr-offset ? saddrp2, #word 0 0 0 0 1 1 0 1 saddr2-offset ? low byte ? high byte ? saddrp1, #word 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 1 saddr1-offset ? low byte ? high byte ? sfrp, #word 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 1 sfr-offset ? low byte ? high byte ? saddrp2, saddrp2 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 saddr2-offset ? saddr2-offset ? saddrp2, saddrp1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 0 1 saddr1-offset ? saddr2-offset ? saddrp1, saddrp2 0 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 saddr2-offset ? saddr1-offset ? saddrp1, saddrp1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 saddr1-offset ? saddr1-offset ? subw ax, #word 0 0 1 0 1 1 1 0 low byte ? high byte ? rp, #word 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1011 low byte ? high byte ? rp, rp 1 0 0 0 1 0 1 0 p 7 p 6 p 5 01p 2 p 1 p 0 ax, saddrp2 0 0 0 1 1 1 1 0 saddr2-offset ? rp, saddrp2 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1000 saddr2-offset ? rp, saddrp1 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1001 saddr1-offset ? saddrp2, rp 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1100 saddr2-offset ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
241 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 subw saddrp1, rp 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1101 saddr1-offset ? rp, sfrp 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1010 sfr-offset ? sfrp, rp 0 1 1 1 1 0 1 0 p 7 p 6 p 5 0 1110 sfr-offset ? saddrp2, #word 0 0 0 0 1 1 1 0 saddr2-offset ? low byte ? high byte ? saddrp1, #word 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 0 saddr1-offset ? low byte ? high byte ? sfrp, #word 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 sfr-offset ? low byte ? high byte ? saddrp2, saddrp2 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 0 saddr2-offset ? saddr2-offset ? saddrp2, saddrp1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 0 saddr1-offset ? saddr2-offset ? saddrp1, saddrp2 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 saddr2-offset ? saddr1-offset ? saddrp1, saddrp1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 saddr1-offset ? saddr1-offset ? cmpw ax, #word 0 0 1 0 1 1 1 1 low byte ? high byte ? rp, #word 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1011 low byte ? high byte ? rp, rp 1 0 0 0 1 1 1 1 p 7 p 6 p 5 01p 2 p 1 p 0 ax, saddrp2 0 0 0 1 1 1 1 1 saddr2-offset ? rp, saddrp2 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1000 saddr2-offset ? rp, saddrp1 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1001 saddr1-offset ? saddrp2, rp 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1100 saddr2-offset ? saddrp1, rp 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1101 saddr1-offset ? rp, sfrp 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1010 sfr-offset ? sfrp, rp 0 1 1 1 1 1 1 1 p 7 p 6 p 5 0 1110 sfr-offset ? saddrp2, #word 0 0 0 0 1 1 1 1 saddr2-offset ? low byte ? high byte ? saddrp1, #word 0 0 1 1 1 1 0 0 0 0 0 0 1 1 1 1 saddr1-offset ? low byte ? high byte ? sfrp, #word 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 sfr-offset ? low byte ? high byte ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
242 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 cmpw saddrp2, saddrp2 0 0 1 0 1 0 1 0 1 0 0 0 1 1 1 1 saddr2-offset ? saddr2-offset ? saddrp2, saddrp1 0 0 1 0 1 0 1 0 1 0 0 1 1 1 1 1 saddr1-offset ? saddr2-offset ? saddrp1, saddrp2 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 saddr2-offset ? saddr1-offset ? saddrp1, saddrp1 0 0 1 0 1 0 1 0 1 0 1 1 1 1 1 1 saddr1-offset ? saddr1-offset ? (8) 24-bit operation instructions: addg, subg mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 addg rg, rg 1 0 0 0 1 0 0 0 1 g 6 g 5 11g 2 g 1 1 rg, #imm24 0 1 1 1 1 0 0 0 1 g 6 g 5 1 1011 low byte ? high byte ? high-w byte ? whl, saddrg2 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 0 saddr2-offset ? whl, saddrg1 0 1 1 1 1 0 0 0 1 1 1 1 1 0 0 1 saddr1-offset ? subg rg, rg 1 0 0 0 1 0 1 0 1 g 6 g 5 11g 2 g 1 1 rg, #imm24 0 1 1 1 1 0 1 0 1 g 6 g 5 1 1011 low byte ? high byte ? high-w byte ? whl, saddrg2 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 0 saddr2-offset ? whl, saddrg1 0 1 1 1 1 0 1 0 1 1 1 1 1 0 0 1 saddr1-offset ? -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
243 chapter 6 instruction set (9) multiplication instructions: mulu, muluw, mulw, divuw, divux mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mulu r1 0000 0101 0000 1r 2 r 1 r 0 r2 0011 1100 0000 0101 0000 1r 2 r 1 r 0 muluw rp 0000 0101 0010 1p 2 p 1 p 0 mulw rp 0000 0101 0011 1p 2 p 1 p 0 divuw r1 0000 0101 0001 1r 2 r 1 r 0 r2 0011 1100 0000 0101 0001 1r 2 r 1 r 0 divux rp 0000 0101 1110 1p 2 p 1 p 0 (10) special operation instructions: macw, macsw, sacw mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 macw byte 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 1 byte ? macsw byte 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 byte ? sacw [tde + ], [whl + ] 0 0 0 0 1 0 0 1 0 1 1 0 0 1 0 0 0 1 0 0 0 0 0 1 0100 0110 --------------------------------------------------------------------------------
244 chapter 6 instruction set (11) increment/decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 inc r1 1100 0r 2 r 1 r 0 r2 0011 1100 1100 0r 2 r 1 r 0 saddr2 0 0 1 0 0 1 1 0 saddr2-offset ? saddr1 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 saddr1-offset ? dec r1 1100 1r 2 r 1 r 0 r2 0011 1100 1100 1r 2 r 1 r 0 saddr2 0 0 1 0 0 1 1 1 saddr2-offset ? saddr1 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 1 saddr1-offset ? incw rp0 0011 1110 0000 1101 rp1 0011 1110 0010 1101 rp2 0011 1110 0100 1101 rp3 0011 1110 0110 1101 vp (rp4) 0 1 0 0 0 1 0 0 up (rp5) 0 1 0 0 0 1 0 1 de (rp6) 0 1 0 0 0 1 1 0 hl (rp7) 0 1 0 0 0 1 1 1 saddrp2 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 saddr2-offset ? saddrp1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 0 saddr1-offset ? decw rp0 0011 1110 0000 1111 rp1 0011 1110 0010 1111 rp2 0011 1110 0100 1111 rp3 0011 1110 0110 1111 vp (rp4) 0 1 0 0 1 1 0 0 up (rp5) 0 1 0 0 1 1 0 1 de (rp6) 0 1 0 0 1 1 1 0 hl (rp7) 0 1 0 0 1 1 1 1 saddrp2 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 saddr2-offset ? saddrp1 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 1 0 0 1 saddr1-offset ? incg rg 0011 1110 1g 6 g 5 1 1101 decg rg 0011 1110 1g 6 g 5 1 1111
245 chapter 6 instruction set (12) adjustment instructions: adjba, adjbs, cvtbw mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 adjba 0000 0101 1111 1110 adjbs 0000 0101 1111 1111 cvtbw 0000 0100 (13) shift/rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 ror r1, n 0 0 1 1 0 0 0 0 0 1 n 2 n 1 n 0 r 2 r 1 r 0 r2, n 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 n 2 n 1 n 0 r 2 r 1 r 0 rol r1, n 0 0 1 1 0 0 0 1 0 1 n 2 n 1 n 0 r 2 r 1 r 0 r2, n 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 n 2 n 1 n 0 r 2 r 1 r 0 rorc r1, n 0 0 1 1 0 0 0 0 0 0 n 2 n 1 n 0 r 2 r 1 r 0 r2, n 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 n 2 n 1 n 0 r 2 r 1 r 0 rolc r1, n 0 0 1 1 0 0 0 1 0 0 n 2 n 1 n 0 r 2 r 1 r 0 r2, n 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 0 n 2 n 1 n 0 r 2 r 1 r 0 shr r1, n 0 0 1 1 0 0 0 0 1 0 n 2 n 1 n 0 r 2 r 1 r 0 r2, n 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 0 n 2 n 1 n 0 r 2 r 1 r 0 shl r1, n 0 0 1 1 0 0 0 1 1 0 n 2 n 1 n 0 r 2 r 1 r 0 r2, n 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 1 1 0 n 2 n 1 n 0 r 2 r 1 r 0 shrw rp, n 0 0 1 1 0 0 0 0 1 1 n 2 n 1 n 0 p 2 p 1 p 0 shlw rp, n 0 0 1 1 0 0 0 1 1 1 n 2 n 1 n 0 p 2 p 1 p 0 ror4 mem3 0 0 0 0 0 1 0 1 1 0 0 0 1 p 2 p 1 p 0 rol4 mem3 0 0 0 0 0 1 0 1 1 0 0 1 1 p 2 p 1 p 0
246 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mov1 cy, saddr2. bit 0 0 0 0 1 0 0 0 0 0 0 0 0 b 2 b 1 b 0 saddr2-offset ? cy, saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 b 2 b 1 b 0 saddr1-offset ? cy, sfr. bit 0 0 0 0 1 0 0 0 0 0 0 0 1 b 2 b 1 b 0 sfr-offset ? cy, x. bit 0 0 0 0 0 0 1 1 0 0 0 0 0 b 2 b 1 b 0 cy, a. bit 0 0 0 0 0 0 1 1 0 0 0 0 1 b 2 b 1 b 0 cy, pswl. bit 0 0 0 0 0 0 1 0 0 0 0 0 0 b 2 b 1 b 0 cy, pswh. bit 0 0 0 0 0 0 1 0 0 0 0 0 1 b 2 b 1 b 0 cy, [tde]. bit 0 0 1 1 1 1 0 1 0 0 0 0 0 b 2 b 1 b 0 cy, [whl]. bit 0 0 1 1 1 1 0 1 0 0 0 0 1 b 2 b 1 b 0 cy, !addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 b 2 b 1 b 0 low address ? high address ? cy, !!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? saddr2. bit, cy 0 0 0 0 1 0 0 0 0 0 0 1 0 b 2 b 1 b 0 saddr2-offset ? saddr1. bit, cy 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 b 2 b 1 b 0 saddr1-offset ? sfr. bit, cy 0 0 0 0 1 0 0 0 0 0 0 1 1 b 2 b 1 b 0 sfr-offset ? x. bit, cy 0 0 0 0 0 0 1 1 0 0 0 1 0 b 2 b 1 b 0 a. bit, cy 0 0 0 0 0 0 1 1 0 0 0 1 1 b 2 b 1 b 0 pswl. bit, cy 0 0 0 0 0 0 1 0 0 0 0 1 0 b 2 b 1 b 0 pswh. bit, cy 0 0 0 0 0 0 1 0 0 0 0 1 1 b 2 b 1 b 0 [tde]. bit, cy 0 0 1 1 1 1 0 1 0 0 0 1 0 b 2 b 1 b 0 [whl]. bit, cy 0 0 1 1 1 1 0 1 0 0 0 1 1 b 2 b 1 b 0 !addr16. bit, cy 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 0 b 2 b 1 b 0 low address ? high address ? !addr24. bit, cy 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? and1 cy, saddr2. bit 0 0 0 0 1 0 0 0 0 0 1 0 0 b 2 b 1 b 0 saddr2-offset ? cy, saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 b 2 b 1 b 0 saddr1-offset ? cy,/saddr2. bit 0 0 0 0 1 0 0 0 0 0 1 1 0 b 2 b 1 b 0 saddr2-offset ? (continued on next page)
247 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 and1 cy,/saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 b 2 b 1 b 0 saddr1-offset ? cy, sfr. bit 0 0 0 0 1 0 0 0 0 0 1 0 1 b 2 b 1 b 0 sfr-offset ? cy,/sfr. bit 0 0 0 0 1 0 0 0 0 0 1 1 1 b 2 b 1 b 0 sfr-offset ? cy, x. bit 0 0 0 0 0 0 1 1 0 0 1 0 0 b 2 b 1 b 0 cy,/x. bit 0 0 0 0 0 0 1 1 0 0 1 1 0 b 2 b 1 b 0 cy, a. bit 0 0 0 0 0 0 1 1 0 0 1 0 1 b 2 b 1 b 0 cy,/a. bit 0 0 0 0 0 0 1 1 0 0 1 1 1 b 2 b 1 b 0 cy, pswl. bit 0 0 0 0 0 0 1 0 0 0 1 0 0 b 2 b 1 b 0 cy,/pswl. bit 0 0 0 0 0 0 1 0 0 0 1 1 0 b 2 b 1 b 0 cy, pswh. bit 0 0 0 0 0 0 1 0 0 0 1 0 1 b 2 b 1 b 0 cy,/pswh. bit 0 0 0 0 0 0 1 0 0 0 1 1 1 b 2 b 1 b 0 cy, [tde]. bit 0 0 1 1 1 1 0 1 0 0 1 0 0 b 2 b 1 b 0 cy,/ [tde]. bit 0 0 1 1 1 1 0 1 0 0 1 1 0 b 2 b 1 b 0 cy, [whl]. bit 0 0 1 1 1 1 0 1 0 0 1 0 1 b 2 b 1 b 0 cy,/ [whl]. bit 0 0 1 1 1 1 0 1 0 0 1 1 1 b 2 b 1 b 0 cy, !addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 0 0 b 2 b 1 b 0 low address ? high address ? cy, /!addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1 0 b 2 b 1 b 0 low address ? high address ? cy, !!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? cy, /!!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 1 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? or1 cy, saddr2. bit 0 0 0 0 1 0 0 0 0 1 0 0 0 b 2 b 1 b 0 saddr2-offset ? cy, saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 b 2 b 1 b 0 saddr1-offset ? cy, /saddr2. bit 0 0 0 0 1 0 0 0 0 1 0 1 0 b 2 b 1 b 0 saddr2-offset ? cy, /saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 b 2 b 1 b 0 saddr1-offset ? cy, sfr. bit 0 0 0 0 1 0 0 0 0 1 0 0 1 b 2 b 1 b 0 sfr-offset ? cy,/sfr. bit 0 0 0 0 1 0 0 0 0 1 0 1 1 b 2 b 1 b 0 sfr-offset ? cy, x. bit 0 0 0 0 0 0 1 1 0 1 0 0 0 b 2 b 1 b 0 cy,/x. bit 0 0 0 0 0 0 1 1 0 1 0 1 0 b 2 b 1 b 0 (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
248 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 or1 cy, a. bit 0 0 0 0 0 0 1 1 0 1 0 0 1 b 2 b 1 b 0 cy,/a. bit 0 0 0 0 0 0 1 1 0 1 0 1 1 b 2 b 1 b 0 cy, pswl. bit 0 0 0 0 0 0 1 0 0 1 0 0 0 b 2 b 1 b 0 cy,/pswl. bit 0 0 0 0 0 0 1 0 0 1 0 1 0 b 2 b 1 b 0 cy, pswh. bit 0 0 0 0 0 0 1 0 0 1 0 0 1 b 2 b 1 b 0 cy,/pswh. bit 0 0 0 0 0 0 1 0 0 1 0 1 1 b 2 b 1 b 0 cy, [tde]. bit 0 0 1 1 1 1 0 1 0 1 0 0 0 b 2 b 1 b 0 cy,/ [tde]. bit 0 0 1 1 1 1 0 1 0 1 0 1 0 b 2 b 1 b 0 cy, [whl]. bit 0 0 1 1 1 1 0 1 0 1 0 0 1 b 2 b 1 b 0 cy,/ [whl]. bit 0 0 1 1 1 1 0 1 0 1 0 1 1 b 2 b 1 b 0 cy, !addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 b 2 b 1 b 0 low address ? high address ? cy,/!addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 1 0 b 2 b 1 b 0 low address ? high address ? cy, !!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? cy,/!!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 0 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? xor1 cy, saddr2. bit 0 0 0 0 1 0 0 0 0 1 1 0 0 b 2 b 1 b 0 saddr2-offset ? cy, saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 b 2 b 1 b 0 saddr1-offset ? cy, sfr. bit 0 0 0 0 1 0 0 0 0 1 1 0 1 b 2 b 1 b 0 sfr-offset ? cy, x. bit 0 0 0 0 0 0 1 1 0 1 1 0 0 b 2 b 1 b 0 cy, a. bit 0 0 0 0 0 0 1 1 0 1 1 0 1 b 2 b 1 b 0 cy, pswl. bit 0 0 0 0 0 0 1 0 0 1 1 0 0 b 2 b 1 b 0 cy, pswh. bit 0 0 0 0 0 0 1 0 0 1 1 0 1 b 2 b 1 b 0 cy, [tde]. bit 0 0 1 1 1 1 0 1 0 1 1 0 0 b 2 b 1 b 0 cy, [whl]. bit 0 0 1 1 1 1 0 1 0 1 1 0 1 b 2 b 1 b 0 cy, !addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 0 0 b 2 b 1 b 0 low address ? high address ? cy, !!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
249 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 not1 saddr2. bit 0 0 0 0 1 0 0 0 0 1 1 1 0 b 2 b 1 b 0 saddr2-offset ? saddr1. bit 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 b 2 b 1 b 0 saddr1-offset ? sfr. bit 0 0 0 0 1 0 0 0 0 1 1 1 1 b 2 b 1 b 0 sfr-offset ? x. bit 0000 0011 0111 0b 2 b 1 b 0 a. bit 0000 0011 0111 1b 2 b 1 b 0 pswl. bit 0 0 0 0 0 0 1 0 0 1 1 1 0 b 2 b 1 b 0 pswh. bit 0 0 0 0 0 0 1 0 0 1 1 1 1 b 2 b 1 b 0 [tde]. bit 0 0 1 1 1 1 0 1 0 1 1 1 0 b 2 b 1 b 0 [whl]. bit 0 0 1 1 1 1 0 1 0 1 1 1 1 b 2 b 1 b 0 !addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 0 b 2 b 1 b 0 low address ? high address ? !!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 1 1 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? cy 0100 0010 set1 saddr2. bit 1 0 1 1 0 b 2 b 1 b 0 saddr2-offset ? saddr1. bit 0 0 1 1 1 1 0 0 1 0 1 1 0 b 2 b 1 b 0 saddr1-offset ? sfr. bit 0 0 0 0 1 0 0 0 1 0 0 0 1 b 2 b 1 b 0 sfr-offset ? x. bit 0000 0011 1000 0b 2 b 1 b 0 a. bit 0000 0011 1000 1b 2 b 1 b 0 pswl. bit 0 0 0 0 0 0 1 0 1 0 0 0 0 b 2 b 1 b 0 pswh. bit 0 0 0 0 0 0 1 0 1 0 0 0 1 b 2 b 1 b 0 [tde]. bit 0 0 1 1 1 1 0 1 1 0 0 0 0 b 2 b 1 b 0 [whl]. bit 0 0 1 1 1 1 0 1 1 0 0 0 1 b 2 b 1 b 0 !addr16. bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 0 b 2 b 1 b 0 low address ? high address ? !!addr24. bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? cy 0100 0001 (continued on next page)
250 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 clr1 saddr2. bit 1 0 1 0 0 b 2 b 1 b 0 saddr2-offset ? saddr1. bit 0 0 1 1 1 1 0 0 1 0 1 0 0 b 2 b 1 b 0 saddr1-offset ? sfr. bit 0 0 0 0 1 0 0 0 1 0 0 1 1 b 2 b 1 b 0 sfr-offset ? x. bit 0000 0011 1001 0b 2 b 1 b 0 a. bit 0000 0011 1001 1b 2 b 1 b 0 pswl. bit 0 0 0 0 0 0 1 0 1 0 0 1 0 b 2 b 1 b 0 pswh. bit 0 0 0 0 0 0 1 0 1 0 0 1 1 b 2 b 1 b 0 [tde]. bit 0 0 1 1 1 1 0 1 1 0 0 1 0 b 2 b 1 b 0 [whl]. bit 0 0 1 1 1 1 0 1 1 0 0 1 1 b 2 b 1 b 0 !addr16.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 0 b 2 b 1 b 0 low address ? high address ? !!addr24.bit 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 0 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? cy 0100 0000 -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
251 chapter 6 instruction set (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 push psw 0100 1001 sfrp 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 1 sfr-offset ? sfr 0000 0111 1101 1011 sfr-offset ? post 0 0 1 1 0 1 0 1 post ? rg 0000 1001 1000 1g 2 g 1 1 pushu post 0 0 1 1 0 1 1 1 post ? pop psw 0100 1000 sfrp 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 sfr-offset ? sfr 0000 0111 1101 1010 sfr-offset ? post 0 0 1 1 0 1 0 0 post ? rg 0000 1001 1001 1g 2 g 1 1 popu post 0 0 1 1 0 1 1 0 post ? movg sp, #imm24 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 low byte ? high byte ? high-w byte ? sp, whl 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 1 whl, sp 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 addwg sp, #word 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 low byte ? high byte ? subwg sp, #word 0 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 low byte ? high byte ? incg sp 0000 0101 1111 1000 decg sp 0000 0101 1111 1001 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
252 chapter 6 instruction set (16) call/return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 call !addr16 0 0 1 0 1 0 0 0 low address ? high address ? !!addr20 0 0 0 0 1 0 0 1 1 1 1 1 hi-w add low address ? high address ? rp 0000 0101 0101 1p 2 p 1 p 0 rg 0000 0101 0101 0g 2 g 1 1 [rp] 0 0 0 0 0 1 0 1 0 1 1 1 1 p 2 p 1 p 0 [rg] 0 0 0 0 0 1 0 1 0 1 1 1 0 g 2 g 1 1 $!addr20 0 0 1 1 1 1 1 1 $addr low ? $addr high ? callf !addr11 1 0 0 1 0 fa ? callt [addr5] 1 1 1 t 4 t 3 t 2 t 1 t 0 brk 0101 1110 brkcs rbn 0000 0101 1101 1e 2 e 1 e 0 ret 0101 0110 reti 0101 0111 retb 0101 1111 retcs !addr16 0 0 1 0 1 0 0 1 low address ? high address ? retcsb !addr16 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 0 low address ? high address ? -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
253 chapter 6 instruction set (17) unconditional branch instruction: br mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 br !addr16 0 0 1 0 1 1 0 0 low address ? high address ? !!addr20 0 0 0 0 1 0 0 1 1 1 1 0 hi-w add low address ? high address ? rp 0000 0101 0100 1p 2 p 1 p 0 rg 0000 0101 0100 0g 2 g 1 1 [rp] 0 0 0 0 0 1 0 1 0 1 1 0 1 p 2 p 1 p 0 [rg] 0 0 0 0 0 1 0 1 0 1 1 0 0 g 2 g 1 1 $addr20 0 0 0 1 0 1 0 0 $addr20 ? $!addr20 0 1 0 0 0 0 1 1 $addr low ? $addr high ? (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 bnz $addr20 1 0 0 0 0 0 0 0 $addr20 ? bne bz $addr20 1 0 0 0 0 0 0 1 $addr20 ? be bnc $addr20 1 0 0 0 0 0 1 0 $addr20 ? bnl bc $addr20 1 0 0 0 0 0 1 1 $addr20 ? bl bnv $addr20 1 0 0 0 0 1 0 0 $addr20 ? bpo bv $addr20 1 0 0 0 0 1 0 1 $addr20 ? bpe bp $addr20 1 0 0 0 0 1 1 0 $addr20 ? bn $addr20 1 0 0 0 0 1 1 1 $addr20 ? blt $addr20 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 $addr20 ? (continued on next page) --------------------------------------------------------------------------------
254 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 bge $addr20 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 $addr20 ? ble $addr20 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 0 $addr20 ? bgt $addr20 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 $addr20 ? bnh $addr20 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 $addr20 ? bh $addr20 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 $addr20 ? bf saddr2. bit, $addr20 0 0 0 0 1 0 0 0 1 0 1 0 0 b 2 b 1 b 0 saddr2-offset ? $addr20 ? saddr1. bit, $addr20 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 b 2 b 1 b 0 saddr1-offset ? $addr20 ? sfr. bit, $addr20 0 0 0 0 1 0 0 0 1 0 1 0 1 b 2 b 1 b 0 sfr-offset ? $addr20 ? x. bit, $addr20 0 0 0 0 0 0 1 1 1 0 1 0 0 b 2 b 1 b 0 $addr20 ? a. bit, $addr20 0 0 0 0 0 0 1 1 1 0 1 0 1 b 2 b 1 b 0 $addr20 ? pswl. bit, $addr20 0 0 0 0 0 0 1 0 1 0 1 0 0 b 2 b 1 b 0 $addr20 ? pswh. bit, $addr20 0 0 0 0 0 0 1 0 1 0 1 0 1 b 2 b 1 b 0 $addr20 ? [tde]. bit, $addr20 0 0 1 1 1 1 0 1 1 0 1 0 0 b 2 b 1 b 0 $addr20 ? [whl]. bit, $addr20 0 0 1 1 1 1 0 1 1 0 1 0 1 b 2 b 1 b 0 $addr20 ? !addr16.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 0 b 2 b 1 b 0 low address ? high address ? $addr20 ? !!addr24.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? $addr20 ? bt saddr2. bit, $addr20 0 1 1 1 0 b 2 b 1 b 0 saddr2-offset ? $addr20 ? saddr1. bit, $addr20 0 0 1 1 1 1 0 0 0 1 1 1 0 b 2 b 1 b 0 saddr1-offset ? $addr20 ? sfr. bit, $addr20 0 0 0 0 1 0 0 0 1 0 1 1 1 b 2 b 1 b 0 sfr-offset ? $addr20 ? x. bit, $addr20 0 0 0 0 0 0 1 1 1 0 1 1 0 b 2 b 1 b 0 $addr20 ? a. bit, $addr20 0 0 0 0 0 0 1 1 1 0 1 1 1 b 2 b 1 b 0 $addr20 ? pswl. bit, $addr20 0 0 0 0 0 0 1 0 1 0 1 1 0 b 2 b 1 b 0 $addr20 ? pswh. bit, $addr20 0 0 0 0 0 0 1 0 1 0 1 1 1 b 2 b 1 b 0 $addr20 ? [tde]. bit, $addr20 0 0 1 1 1 1 0 1 1 0 1 1 0 b 2 b 1 b 0 $addr20 ? [whl]. bit, $addr20 0 0 1 1 1 1 0 1 1 0 1 1 1 b 2 b 1 b 0 $addr20 ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
255 chapter 6 instruction set -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 bt !addr16.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 0 b 2 b 1 b 0 low address ? high address ? $addr20 ? !!addr24.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 0 1 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? $addr20 ? btclr saddr2, bit, $addr20 0 0 0 0 1 0 0 0 1 1 0 1 0 b 2 b 1 b 0 saddr2-offset ? $addr20 ? saddr1. bit, $addr20 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 b 2 b 1 b 0 saddr1-offset ? $addr20 ? sfr. bit, $addr20 0 0 0 0 1 0 0 0 1 1 0 1 1 b 2 b 1 b 0 sfr-offset ? $addr20 ? x. bit, $addr20 0 0 0 0 0 0 1 1 1 1 0 1 0 b 2 b 1 b 0 $addr20 ? a. bit, $addr20 0 0 0 0 0 0 1 1 1 1 0 1 1 b 2 b 1 b 0 $addr20 ? pswl. bit, $addr20 0 0 0 0 0 0 1 0 1 1 0 1 0 b 2 b 1 b 0 $addr20 ? pswh. bit, $addr20 0 0 0 0 0 0 1 0 1 1 0 1 1 b 2 b 1 b 0 $addr20 ? [tde]. bit, $addr20 0 0 1 1 1 1 0 1 1 1 0 1 0 b 2 b 1 b 0 $addr20 ? [whl]. bit, $addr20 0 0 1 1 1 1 0 1 1 1 0 1 1 b 2 b 1 b 0 $addr20 ? !addr16.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 0 b 2 b 1 b 0 low address ? high address ? $addr20 ? !!addr24.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 1 1 b 2 b 1 b 0 high-w address ? low address ? high address ? $addr20 ? bfset saddr2. bit, $addr20 0 0 0 0 1 0 0 0 1 1 0 0 0 b 2 b 1 b 0 saddr2-offset ? $addr20 ? saddr1. bit, $addr20 0 0 1 1 1 1 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 b 2 b 1 b 0 saddr1-offset ? $addr20 ? sfr. bit, $addr20 0 0 0 0 1 0 0 0 1 1 0 0 1 b 2 b 1 b 0 sfr-offset ? $addr20 ? x. bit, $addr20 0 0 0 0 0 0 1 1 1 1 0 0 0 b 2 b 1 b 0 $addr20 ? a. bit, $addr20 0 0 0 0 0 0 1 1 1 1 0 0 1 b 2 b 1 b 0 $addr20 ? pswl. bit, $addr20 0 0 0 0 0 0 1 0 1 1 0 0 0 b 2 b 1 b 0 $addr20 ? pswh. bit, $addr20 0 0 0 0 0 0 1 0 1 1 0 0 1 b 2 b 1 b 0 $addr20 ? [tde]. bit, $addr20 0 0 1 1 1 1 0 1 1 1 0 0 0 b 2 b 1 b 0 $addr20 ? [whl]. bit, $addr20 0 0 1 1 1 1 0 1 1 1 0 0 1 b 2 b 1 b 0 $addr20 ? (continued on next page) -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
256 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 bfset !addr16.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 0 0 b 2 b 1 b 0 low address ? high address ? $addr20 ? !!addr24.bit, $addr20 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 1 1 0 0 1 b 2 b 1 b 0 high-w address ? low address ? high address ? $addr20 ? dbnz b, $addr20 0 0 1 1 0 0 1 1 $addr20 ? c, $addr20 0 0 1 1 0 0 1 0 $addr20 ? saddr2, $addr20 0 0 1 1 1 0 1 1 saddr2-offset ? $addr20 ? saddr1, $addr20 0 0 1 1 1 1 0 0 0 0 1 1 1 0 1 1 saddr1-offset ? $addr20 ? (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 mov stbc, #byte 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 #byte ? #byte ? wdm, #byte 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 #byte ? #byte ? location locaddr 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 1 locaddr1 ? locaddrh ? sel rbn 0000 0101 1010 1e 2 e 1 e 0 rbn. alt 0 0 0 0 0 1 0 1 1 0 1 1 1 e 2 e 1 e 0 swrs 0000 0101 1111 1100 nop 0000 0000 ei 0100 1011 di 0100 1010 -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- --------------------------------------------------------------------------------
257 chapter 6 instruction set (20) special instructions: chkl, chkla mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 chkl sfr 0000 0111 1100 1000 sfr address ? chkla sfr 0000 0111 1100 1001 sfr address ? caution the chkl and chkla instructions are not available in the m pd784216, 784216y, 784218, 784218y, 784225, 784225y, 784937 subseries. do not execute these instructions. if these instructions are executed, the following operations will result. ? chkl instruction ....... after the pin levels of the output pins are read two times, they are exclusive-ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1). ? chkla instruction .... after the pin levels of output pins are read two times, they are exclusive- ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1) along with that the result is stored in the a register. (21) string instructions: movtblw, movm, movbk, xchm, xchbk, cmpme, cmpbke, cmpmne, cmpbkne, cmpmc, cmpbkc, cmpmnc, cmpbknc mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 movtblw !addr8, byte 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 low address ? byte ? movm [tde +], a 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 [tde C], a 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 movbk [tde +], [whl +] 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 0 [tde C], [whl C] 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 0 xchm [tde +], a 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 1 [tde C], a 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 1 xchbk [tde +], [whl +] 0 0 0 1 0 1 0 1 0 0 1 0 0 0 0 1 [tde C], [whl C] 0 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 cmpme [tde +], a 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 [tde C], a 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 0 cmpbke [tde +], [whl +] 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 [tde C], [whl C] 0 0 0 1 0 1 0 1 0 0 1 1 0 1 0 0 cmpmne [tde +], a 0 0 0 1 0 1 0 1 0 0 0 0 0 1 0 1 [tde C], a 0 0 0 1 0 1 0 1 0 0 0 1 0 1 0 1 (continued on next page) --------------------------------------------------------------------------------
258 chapter 6 instruction set mnemonic operands operation code b1 b2 b3 b4 b5 b6 b7 cmpbkne [tde +], [whl +] 0 0 0 1 0 1 0 1 0 0 1 0 0 1 0 1 [tde C], [whl C] 0 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 cmpmc [tde +], a 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 1 [tde C], a 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 1 cmpbkc [tde +], [whl +] 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 [tde C], [whl C] 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 cmpmnc [tde +], a 0 0 0 1 0 1 0 1 0 0 0 0 0 1 1 0 [tde C], a 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 cmpbknc [tde +], [whl +] 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 [tde C], [whl C] 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 0
259 chapter 6 instruction set 6.5 number of instruction clocks 6.5.1 execution time of instruction the execution time for instructions is shown as the number of clocks of f clk . the cpu in the 78k/iv series has an instruction queue, so that another instruction can be prefetched in parallel while one instruction is executed. consequently, the actual execution time of an instruction is dependent on the preceding instruction. the execution time of an instruction also changes with the number of wait states used for memory access. therefore, the accurate execution time of the program cannot be calculated by merely adding the number of execution clocks of instructions. the minimum number of execution clocks is shown for instructions except those used for branch operation, such as br, call, and ret instructions. for the branch instructions, the number of clocks slightly more than the minimum value is shown. 6.5.2 definitions for clocks column (1) internal rom the number of clocks set to 1 if the data to be accessed by an instruction is stored in the internal rom and if the ifch bit, which is bit 7 of the memory mapping mode register (mm), is shown. if the ifch bit is cleared to 0, refer to the column of pram, emem, or sfr. (2) iram the number of clocks if the data to be accessed by an instruction is stored in the internal high-speed ram (the area of addresses fd00h through feffh when location 0 instruction is executed, and the area of ffd00h through ffeffh when location 0fh instruction is executed) is shown. the m pd784915 subseries is fixed to the location instruction. (3) pram/emem/sfr the number of clocks if the data to be accessed by an instruction is stored in an area of the internal ram which is not iram, in the external memory (including the external sfr), or in the sfr area is shown. (4) others the number of clocks if no data is accessed by an instruction is shown.
260 chapter 6 instruction set 6.5.3 explanation of clocks column (1) number of clocks for accessing word data ? the number of clocks shown in the pram, emem, and sfr columns is when the bus width is 16 bits and when data is located at an even address. if the bus width is 8 bits, or if data is located at an odd address even though the bus width is 16 bits, add 4 to the number of clocks shown in the table. note that the width of the internal ram is 16 bits. also, if word data of the internal rom is located at an odd address, add 4 to the number of clocks. ? if word data is saved to or restored from an odd address by a stack manipulation instruction marked n, add 4 to the coefficient of n. (2) number of clocks for accessing 3-byte data the number of clocks shown in the pram, emem, or sfr column is used when the bus width is 16 bits. if the bus width is 8 bits, and if data is located at an odd address even though the bus width is 16 bits, add 4 to the number of clocks shown in the table. note that the bus width of the internal ram is 16 bits. (3) if two types of numbers of clocks are shown with each delimited by / from the other if two types of numbers of clocks are shown with each delimited by / from the other, two types of numbers of bytes are shown for that instruction with each delimited by / from the other. the execution time of this kind of instruction is the number of clocks shown at the same side as the number of bytes. (4) when n is shown in clocks column ? when the macw, macsw, and movtblw instructions are used, the number specified by operand byte substitutes for n. ? in the case of the sacw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, and cmpbknc instructions, the value set to the c register on starting execution of the instruction substitutes for n. this number of clocks is the value when the instruction execution is not stopped by an interrupt or macro service. ? when the shift or rotate instruction is used, the number of bits to be shifted or rotated substitutes for n. ? when the stack manipulation instruction is used, the number of registers to be saved to the stack or restored from the stack substitutes for n.
261 chapter 6 instruction set 6.5.4 list of number of clocks (1) 8-bit data transfer instruction: mov (1/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others mov r, #byte 2/3 C 2/3 C C saddr, #byte 3/4 3/4 7 sfr, #byte 3 C 7 !addr16, #byte 5 C 7 9 !!addr24, #byte 6 C 8 10 r, r 2/3 C 2/3 C a, r 1/2 a, saddr2 2 3 7 r, saddr 3 4 8 saddr2, a 2 2 6 saddr, r 3 4 8 a, sfr 2 C 7 r, sfr 3 8 sfr, a 2 6 sfr, r 3 8 saddr, saddr 4 6 14 r, !addr16 4 9 7 9 !addr16, r 4 C 6 8 r, !!addr24 5 10 8 10 !!addr24, r 5 C 7 9 a, [saddrp] 2/3 9/10 7/8 9/10 a, [%saddrg] 3/4 14/15 12/13 14/15 a, [tde +] 1 9 7 9 a, [whl +] 1 a, [tde C] 1 a, [whl C] 1 a, [tde] 1 8 6 8 a, [whl] 1 a, [vvp] 2 9 7 9 a, [uup] 2 a, [tde + byte] 3 10 8 10 a, [sp + byte] 3 11 9 11
262 chapter 6 instruction set (2/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others mov a, [whl + byte] 3 10 8 10 C a, [uup + byte] 3 a, [vvp + byte] 3 a, imm24[de] 5 12 10 12 a, imm24[a] 5 a, imm24[hl] 5 a, imm24[b] 5 a, [tde + a] 2 10 8 10 a, [whl + a] 2 a, [tde + b] 2 a, [whl + b] 2 a, [vvp + de] 2 a, [vvp + hl] 2 a, [tde + c] 2 a, [whl + c] 2 [saddrp], a 2/3 C 6/7 8/9 [%saddrg], a 3/4 12/13 14/15 [tde +], a 1 8 10 [whl +], a 1 [tde C], a 1 [whl C], a 1 [tde], a 1 5 7 [whl], a 1 [vvp], a 2 7 9 [uup], a 2 [tde + byte], a 3 8 10 [sp + byte], a 3 9 11 [whl + byte], a 3 8 10 [uup + byte], a 3 [vvp + byte], a 3 imm24[de], a 5 10 12 imm24[a], a 5 imm24[hl], a 5 imm24[b], a 5
263 chapter 6 instruction set (3/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others mov [tde + a], a 2 C 8 10 C [whl + a], a 2 [tde + b], a 2 [whl + b], a 2 [vvp + de], a 2 [vvp + hl], a 2 [tde + c], a 2 [whl + c], a 2 pswl, #byte 3 C C 7 pswh, #byte 3 pswl, a 2 6 pswh, a 2 a, pswl 2 7 a, pswh 2 r3, #byte 3 3 a, r3 2 4 r3, a 2 3
264 chapter 6 instruction set (2) 16-bit data transfer instruction: movw (1/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others movw rp, #word 3 C 3 C C saddrp, #word 4/5 4 8 sfrp, #word 4 C !addr16, #word 6 8 10 !!addr24, #word 7 9 11 rp, rp 2 2 C ax, saddrp2 2 3 7 rp, saddrp 3 4 8 saddrp2, ax 2 2 6 saddrp, rp 3 3 7 ax, sfrp 2 C 7 rp, sfrp 3 8 sfrp, ax 2 6 sfrp, rp 3 7 saddrp, saddrp 4 6 14 rp, !addr16 4 9 7 9 !addr16, rp 4 C 6 8 rp, !!addr24 5 10 8 10 !!addr24, rp 5 C 7 9 ax, [saddrp] 3/4 10/11 8/9 10/11 ax, [%saddrg] 3/4 14/15 12/13 14/15 ax, [tde +] 2 11 9 11 ax, [whl +] 2 ax, [tde C] 2 ax, [whl C] 2 ax, [tde] 2 9 7 9 ax, [whl] 2 ax, [vvp] 2 ax, [uup] 2 ax, [tde + byte] 3 10 8 10 ax, [sp + byte] 3 11 9 11 ax, [whl + byte] 3 10 8 10 ax, [uup + byte] 3 ax, [vvp + byte] 3
265 chapter 6 instruction set (2/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others movw ax, imm24[de] 5 12 10 12 C ax, imm24[a] 5 ax, imm24[hl] 5 ax, imm24[b] 5 ax, [tde + a] 2 10 8 10 ax, [whl + a] 2 ax, [tde + b] 2 ax, [whl + b] 2 ax, [vvp + de] 2 ax, [vvp + hl] 2 ax, [tde + c] 2 ax, [whl + c] 2 [saddrp], ax 3/4 C 8/9 10/11 [%saddrg], ax 3/4 12/13 14/15 [tde +], ax 2 9 11 [whl +], ax 2 [tde C], ax 2 [whl C], ax 2 [tde], ax 2 7 9 [whl], ax 2 [vvp], ax 2 [uup], ax 2 [tde + byte], ax 3 8 10 [sp + byte], ax 3 9 11 [whl + byte], ax 3 8 10 [uup + byte], ax 3 [vvp + byte], ax 3 imm24[de], ax 5 10 12 imm24[a], ax 5 imm24[hl], ax 5 imm24[b], ax 5
266 chapter 6 instruction set (3/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others movw [tde + a], ax 2 C 8 10 C [whl + a], ax 2 [tde + b], ax 2 [whl + b], ax 2 [vvp + de], ax 2 [vvp + hl], ax 2 [tde + c], ax 2 [whl + c], ax 2
267 chapter 6 instruction set (3) 24-bit data transfer instruction: movg (1/2) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others movg rg, #imm24 5 C 5 C C rg, rg 2 4 rg, !!addr24 5 17 13 17 !!addr24, rg 5 C 12 16 rg, saddrg 3 9 17 saddrg, rg 3 7 15 whl, [%saddrg] 3/4 21/22 17/18 21/22 [%saddrg], whl 3/4 C whl, [tde +] 2 19 15 19 whl, [tde C] 2 whl, [tde] 2 16 12 16 whl, [whl] 2 whl, [vvp] 2 whl, [uup] 2 whl, [tde + byte] 3 17 13 17 whl, [sp + byte] 3 18 14 18 whl, [whl + byte] 3 17 13 17 whl, [uup + byte] 3 whl, [vvp + byte] 3 whl, imm24[de] 5 19 15 19 whl, imm24[a] 5 whl, imm24[hl] 5 whl, imm24[b] 5 whl, [tde + a] 2 17 13 17 whl, [whl + a] 2 whl, [tde + b] 2 whl, [whl + b] 2 whl, [vvp + de] 2 whl, [vvp + hl] 2 whl, [tde + c] 2 whl, [whl + c] 2
268 chapter 6 instruction set (2/2) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others movg [tde +], whl 2 C 15 19 C [tde C], whl 2 [tde], whl 2 12 16 [whl], whl 2 [vvp], whl 2 [uup], whl 2 [tde + byte], whl 3 13 17 [sp + byte], whl 3 14 18 [whl + byte], whl 3 13 17 [uup + byte], whl 3 [vvp + byte], whl 3 imm24[de], whl 5 15 19 imm24[a], whl 5 imm24[hl], whl 5 imm24[b], whl 5 [tde + a], whl 2 13 17 [whl + a], whl 2 [tde + b], whl 2 [whl + b], whl 2 [vvp + de], whl 2 [vvp + hl], whl 2 [tde + c], whl 2 [whl + c], whl 2
269 chapter 6 instruction set (4) 8-bit data exchange instruction: xch mnemonic operands bytes clocks internal rom iram pram/emem/sfr others xch r, r 2/3 C 4 C C a, r 1/2 4/5 a, saddr2 2 5 13 r, saddr 3 6 14 r, sfr 3 C 14 saddr, saddr 4 8 24 r, !addr16 4 11 15 r, !!addr24 5 a, [saddrp] 2/3 8/9 10/11 a, [%saddrg] 3/4 17/18 21/22 a, [tde +] 2 14 18 a, [whl +] 2 a, [tde C] 2 a, [whl C] 2 a, [tde] 2 12 16 a, [whl] 2 a, [vvp] 2 a, [uup] 2 a, [tde + byte] 3 13 17 a, [sp + byte] 3 14 18 a, [whl + byte] 3 13 17 a, [uup + byte] 3 a, [vvp + byte] 3 a, imm24[de] 5 15 19 a, imm24[a] 5 a, imm24[hl] 5 a, imm24[b] 5 a, [tde + a] 2 13 17 a, [whl + a] 2 a, [tde + b] 2 a, [whl + b] 2 a, [vvp + de] 2 a, [vvp + hl] 2 a, [tde + c] 2 a, [whl + c] 2
270 chapter 6 instruction set (5) 16-bit data exchange instruction: xchw mnemonic operands bytes clocks internal rom iram pram/emem/sfr others xchw rp, rp 2 C 4 C C ax, saddrp2 2 5 13 rp, saddrp 3 6 14 rp, sfrp 3 C 14 ax, [saddrp] 3/4 13/14 17/18 ax, [%saddrg] 3/4 17/18 21/22 ax, !addr16 4 3 3 ax, !!addr24 5 4 4 saddrp, saddrp 4 8 24 ax, [tde +] 2 14 18 ax, [whl +] 2 ax, [tde C] 2 ax, [whl C] 2 ax, [tde] 2 12 16 ax, [whl] 2 ax, [vvp] 2 ax, [uup] 2 ax, [tde + byte] 3 13 17 ax, [sp + byte] 3 14 18 ax, [whl + byte] 3 13 17 ax, [uup + byte] 3 ax, [vvp + byte] 3 ax, imm24[de] 5 15 19 ax, imm24[a] 5 ax, imm24[hl] 5 ax, imm24[b] 5 ax, [tde + a] 2 13 17 ax, [whl + a] 2 ax, [tde + b] 2 ax, [whl + b] 2 ax, [vvp + de] 2 ax, [vvp + hl] 2 ax, [tde + c] 2 ax, [whl + c] 2
271 chapter 6 instruction set (6) 8-bit operation instructions: add, addc, sub, subc, and, or, xor, cmp (1/5) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others add a, #byte 2 C 2 C C addc r, #byte 3 4 sub saddr, #byte 3/4 6/7 12/13 subc sfr, #byte 4 C 13 and r, r 2/3 3/4 C or a, saddr2 4 3 7 xor r, saddr 3 4 8 saddr, r 3 8 14 r, sfr 3 C 8 sfr, r 3 C 14 saddr, saddr 4 8 18 a, [saddrp] 3/4 11/12 9/10 11/12 a, [%saddrg] 3/4 15/16 13/14 15/16 [saddrp], a 3/4 C 11/12 15/16 [%saddrg], a 3/4 15/16 19/20 a, !addr16 4 10 8 10 a, !!addr24 5 11 9 11 !addr16, a 4 C 10 14 !!addr24, a 5 11 15 a, [tde +] 1 11 9 11 a, [whl +] 1 a, [tde C] 1 a, [whl C] 1 a, [tde] 1 10 8 10 a, [whl] 1 a, [vvp] 2 a, [uup] 2 a, [tde + byte] 3 12 10 12 a, [sp + byte] 3 a, [whl + byte] 3 a, [uup + byte] 3 a, [vvp + byte] 3
272 chapter 6 instruction set (2/5) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others add a, imm24[de] 5 13 11 13 C addc a, imm24[a] 5 sub a, imm24[hl] 5 subc a, imm24[b] 5 and a, [tde + a] 2 11 9 11 or a, [whl + a] 2 xor a, [tde + b] 2 a, [whl + b] 2 a, [vvp + de] 2 a, [vvp + hl] 2 a, [tde + c] 2 a, [whl + c] 2 [tde +], a 1 C 10 14 [whl +], a 1 [tde C], a 1 [whl C], a 1 [tde], a 1 [whl], a 1 [vvp], a 2 [uup], a 2 [tde + byte], a 3 13 17 [sp + byte], a 3 [whl + byte], a 3 [uup + byte], a 3 [vvp + byte], a 3 imm24[de], a 5 14 18 imm24[a], a 5 imm24[hl], a 5 imm24[b], a 5
273 chapter 6 instruction set (3/5) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others add [tde + a], a 2 C 12 16 C addc [whl + a], a 2 sub [tde + b], a 2 subc [whl + b], a 2 and [vvp + de], a 2 or [vvp + hl], a 2 xor [tde + c], a 2 [whl + c], a 2
274 chapter 6 instruction set (4/5) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others cmp a, #byte 2 C 2 C C r, #byte 3 4 saddr, #byte 3/4 4/5 8/9 sfr, #byte 4 C 9 r, r 2/3 3/4 C a, saddr2 4 3 7 r, saddr 3 4 8 saddr, r 3 6 10 r, sfr 3 C 9 sfr, r 3 10 saddr, saddr 4 6 14 a, [saddrp] 3/4 11/12 9/10 11/12 a, [%saddrg] 3/4 15/16 13/14 15/16 [saddrp], a 3/4 11/12 9/10 11/12 [%saddrg], a 3/4 15/16 13/14 15/16 a, !addr16 4 10 8 10 a, !!addr24 5 11 9 11 !addr16, a 4 10 8 10 !!addr24, a 5 11 9 11 a, [tde +] 1 11 9 11 a, [whl +] 1 a, [tde C] 1 a, [whl C] 1 a, [tde] 1 10 8 10 a, [whl] 1 a, [vvp] 2 a, [uup] 2 a, [tde + byte] 3 12 10 12 a, [sp + byte] 3 a, [whl + byte] 3 a, [uup + byte] 3 a, [vvp + byte] 3 a, imm24[de] 5 13 11 13 a, imm24[a] 5 a, imm24[hl] 5 a, imm24[b] 5
275 chapter 6 instruction set (5/5) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others cmp a, [tde + a] 2 11 9 11 C a, [whl + a] 2 a, [tde + b] 2 a, [whl + b] 2 a, [vvp + de] 2 a, [vvp + hl] 2 a, [tde + c] 2 a, [whl + c] 2 [tde +], a 1 10 8 10 [whl +], a 1 [tde C], a 1 [whl C], a 1 [tde], a 1 [whl], a 1 [vvp], a 2 [uup], a 2 [tde + byte], a 3 13 11 13 [sp + byte], a 3 [whl + byte], a 3 [uup + byte], a 3 [vvp + byte], a 3 imm24[de], a 5 14 12 14 imm24[a], a 5 imm24[hl], a 5 imm24[b], a 5 [tde + a], a 2 12 10 12 [whl + a], a 2 [tde + b], a 2 [whl + b], a 2 [vvp + de], a 2 [vvp + hl], a 2 [tde + c], a 2 [whl + c], a 2
276 chapter 6 instruction set (7) 16-bit operation instructions: addw, subw, cmpw mnemonic operands bytes clocks internal rom iram pram/emem/sfr others addw ax, #word 3 C 3 C C subw rp, #word 4 5 rp, rp 2 3 ax, saddrp2 2 7 rp, saddrp 3 5 9 saddrp, rp 3 8 14 rp, sfrp 3 C 9 sfrp, rp 3 C 13 saddrp, #word 4/5 7/8 sfrp, #word 5 C 14 saddrp, saddrp 4 8 20 cmpw ax, #word 3 C 3 C C rp, #word 4 5 rp, rp 2 3 ax, saddrp2 2 7 rp, saddrp 3 5 9 saddrp, rp 3 rp, sfrp 3 C sfrp, rp 3 saddrp, #word 4/5 5/6 9 sfrp, #word 5 C 10 saddrp, saddrp 4 6
277 chapter 6 instruction set (8) 24-bit operation instructions: addg, subg mnemonic operands bytes clocks internal rom iram pram/emem/sfr others addg rg, rg 2 C 6 C C subg rg, #imm24 5 8 whl, saddrg 3 13 19 (9) multiplication instructions: mulu, muluw, mulw, divuw, divux mnemonic operands bytes clocks internal rom iram pram/emem/sfr others mulu r 2/3 C 11/12 C C muluw rp 2 C 15 C C mulw rp 2 C 14 C C divuw r 2/3 C 23/24 C C divux rp 2 C 43 C C (10) special operation instructions: macw, macsw, sacw mnemonic operands bytes clocks internal rom iram pram/emem/sfr others macw byte 3 C 5 + 21n C C macsw byte 3 C 5 + 21n C C sacw [tde +], [whl +] 4 C 4 + 19n 4 + 23n C
278 chapter 6 instruction set (11) increment/decrement instructions: inc, dec, incw, decw, incg, decg mnemonic operands bytes clocks internal rom iram pram/emem/sfr others inc r 1/2 C 2/3 C C dec saddr 2/3 5/6 11/12 incw rp 2/1 C 3/2 C C decw saddrp 3/4 6/7 12/13 incg rg 2C4CC decg (12) adjustment instructions: adjba, adjbs, cvtbw mnemonic operands bytes clocks internal rom iram pram/emem/sfr others adjba 2C5CC adjbs 2C5CC cvtbw 1C3CC (13) shift/rotate instructions: ror, rol, rorc, rolc, shr, shl, shrw, shlw, ror4, rol4 mnemonic operands bytes clocks internal rom iram pram/emem/sfr others ror r, n 2/3 C 5 + n/6 + n C C rol rorc rolc shr shl shrw rp, n 2 C 5 + n C C shlw ror4 mem3 2 C 11 15 C rol4
279 chapter 6 instruction set (14) bit manipulation instructions: mov1, and1, or1, xor1, not1, set1, clr1 (1/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others mov1 cy, saddr.bit 3/4 C 6/7 10/11 C cy, sfr.bit 3 C 10 cy, x.bit 2 5 C cy, a.bit 2 cy, pswl.bit 2 C 5 cy, pswh.bit 2 cy, [tde].bit 2 11 9 11 cy, [whl].bit 2 cy, !addr16.bit 5 16 14 16 cy, !!addr24.bit 6 saddr.bit, cy 3/4 C 5/6 13/14 sfr.bit, cy 3 C 13 x.bit, cy 2 6 C a.bit, cy 2 pswl.bit, cy 2 C 8 pswh.bit, cy 2 7 [tde].bit, cy 2 10 14 [whl].bit, cy 2 !addr16.bit, cy 5 13 15 !!addr24.bit, cy 6
280 chapter 6 instruction set (2/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others and1 cy, saddr.bit 3/4 C 6/7 10/11 C or1 cy, /saddr.bit 3/4 cy, sfr.bit 3 C 10 cy, /sfr.bit 3 cy, x.bit 2 5 C cy, /x.bit 2 cy, a.bit 2 cy, /a.bit 2 cy, pswl.bit 2 cy, /pswl.bit 2 cy, pswh.bit 2 cy, /pswh.bit 2 cy, [tde].bit 2 11 9 11 cy, /[tde].bit 2 cy, [whl].bit 2 cy, /[whl].bit 2 cy, !addr16.bit 5 16 14 16 cy, /!addr16.bit 5 cy, !!addr24.bit 6 cy, /!!addr24.bit 6 xor1 cy, saddr.bit 3/4 C 6/7 10/11 cy, /sfr.bit 3 C 10 cy, x.bit 2 5 C cy, a.bit 2 cy, pswl.bit 2 C 5 cy, pswh.bit 2 cy, [tde].bit 2 11 9 11 cy, [whl].bit 2 cy, !addr16.bit 5 16 14 16 cy, !!addr24.bit 6
281 chapter 6 instruction set (3/3) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others not1 saddr.bit 3/4 C 5/6 13/14 C sfr.bit 3 C 13 x.bit 2 5 C a.bit 2 pswl.bit 2 C 7 pswh.bit 2 6 [tde].bit 2 10 14 [whl].bit 2 !addr16.bit 5 13 15 !!addr24.bit 6 cy 1 C 2 set1 saddr.bit 2/3 4/5 12/13 clr1 sfr.bit 3 C 13 x.bit 2 5 C a.bit 2 pswl.bit 2 C 7 pswh.bit 2 6 [tde].bit 2 10 14 [whl].bit 2 !addr16.bit 5 13 15 !!addr24.bit 6 cy 1 C 2
282 chapter 6 instruction set (15) stack manipulation instructions: push, pushu, pop, popu, movg, addwg, subwg, incg, decg mnemonic operands bytes clocks internal rom iram pram/emem/sfr others push psw 1 C 5 7 C sfrp 3 10 14 sfr 3 post 2 4 + 5n 4 + 7n rg 2 12 16 pushu post 2 C 6 + 5n 6 + 7n C pop psw 1 8 7 9 C sfrp 3 15 14 16 sfr 3 post 2 4 + 8n 4 + 6n 4 + 8n rg 2 17 13 17 popu post 2 7 + 8n 7 + 6n 7 + 8n C movg sp, #imm24 5 C C C 5 sp, whl 2 whl, sp 2 addwg sp, #word 4 C C C 5 subwg incg sp 2CCC5 decg
283 chapter 6 instruction set (16) call/return instructions: call, callf, callt, brk, brkcs, ret, reti, retb, retcs, retcsb mnemonic operands bytes clocks internal rom iram pram/emem/sfr others call !addr16 3 C 19 23 C !!addr20 4 C 22 26 rp 2 C 20 24 rg 2 C 22 26 [rp] 2 30 note 24 30 [rg] 2 37 note 29 37 $!addr20 3 C 19 23 callf !addr11 2 C 19 23 C callt [addr5] 1 28 note 22 28 C brk 1 C 23 29 C brkcs rbn 2 C C C 13 ret 1211721C reti 1221822C retb 1211721C retcs !addr16 3 C C C 14 retcsb !addr16 4 C C C 14 note when the stack is pram or emem
284 chapter 6 instruction set (17) unconditional branch instruction: br mnemonic operands bytes clocks internal rom iram pram/emem/sfr others br !addr16 3 C C C 11 !!addr20 4 C C C 12 rp 2CCC11 rg 2CCC12 [rp] 2 16 14 16 C [rg] 2 22 18 22 C $addr20 2 C C C 10 $!addr20 3 C C C 11
285 chapter 6 instruction set (18) conditional branch instructions: bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz (1/4) mnemonic operands bytes clocks branches internal rom iram pram/emem/sfr others bnz $addr20 2 3 C C C 10 bne bz $addr20 2 3 C C C 10 be bnc $addr20 2 3 C C C 10 bnl bc $addr20 2 3 C C C 10 bl bnv $addr20 2 3 C C C 10 bpo bv $addr20 2 3 C C C 10 bpe bp $addr20 2 3 C C C 10 bn blt $addr20 3 4 C C C 11 bge $addr20 3 4 C C C 11 ble $addr20 3 4 C C C 11 bgt $addr20 3 4 C C C 11 bnh $addr20 3 4 C C C 11 bh $addr20 3 4 C C C 11 not branch
286 chapter 6 instruction set (2/4) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others bf saddr.bit, $addr20 4/5 C 14/15 18 C C 7/8 11 C sfr.bit, $addr20 4 C C 18 C CC11C x.bit, $addr20 3 C 13 C C C6CC a.bit, $addr20 3 C 13 C C C6CC pswl.bit, $addr20 3 C C 13 C CC6C pswh.bit, $addr20 3 C C 13 C CC6C mem2.bit, $addr20 3 19 17 19 C 12 10 12 C !addr16.bit, $addr20 6 C 22 24 C C1517C !!addr24.bit, $addr20 7 C 22 24 C C1517C remark the number of clocks differs depending on the following cases. therefore, two types of numbers of clocks are shown for each operand with one type shown at the top and the other at the bottom. top : branches (internal rom high-speed fetch, etc.) bottom : does not branch
287 chapter 6 instruction set (3/4) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others bt saddr.bit, $addr20 3/4 C 13/14 17 C C 6/7 10 C sfr.bit, $addr20 4 C C 18 C CC11C x.bit, $addr20 3 C 13 C C C6CC a.bit, $addr20 3 C 13 C C C6CC pswl.bit, $addr20 3 C C 13 C CC6C pswh.bit, $addr20 3 C C 13 C CC6C mem2.bit, $addr20 3 19 17 19 C 12 10 12 C !addr16.bit, $addr20 6 C 22 24 C C1517C !!addr24.bit, $addr20 7 C 22 24 C C1517C remark the number of clocks differs depending on the following cases. therefore, two types of numbers of clocks are shown for each operand with one type shown at the top and the other at the bottom. top : branches (internal rom high-speed fetch, etc.) bottom : does not branch
288 chapter 6 instruction set (4/4) mnemonic operands bytes clocks internal rom iram pram/emem/sfr others btclr saddr.bit, $addr20 4/5 C 16/17 24 C bfset C 7/8 15 C sfr.bit, $addr20 4 C C 24 C CC15C x.bit, $addr20 3 C 15 C C C6CC a.bit, $addr20 3 C 15 C C C6CC pswl.bit, $addr20 3 C C 15 C CC6C pswh.bit, $addr20 3 C C 16 C CC6C mem2.bit, $addr20 3 C 21 25 C C1216C !addr16.bit, $addr20 6 C 24 26 C C1517C !!addr24.bit, $addr20 7 C 24 26 C C1517C dbnz b, $addr20 2 12 C C C 4CCC c, $addr20 2 12 C C C 4CCC saddr, $addr20 3 21 17 21 C 555C 422 18 22 C 666C remark the number of clocks differs depending on the following cases. therefore, two types of numbers of clocks are shown for each operand with one type shown at the top and the other at the bottom. top : branches (internal rom high-speed fetch, etc.) bottom : does not branch
289 chapter 6 instruction set (19) cpu control instructions: mov, location, sel, swrs, nop, ei, di mnemonic operands bytes clocks internal rom iram pram/emem/sfr others mov stbc, #byte 4 C C C 13 wdm, #byte 4 location locaddr 4 C C C 13 sel rbn 2 C C C 3 rbn, alt 2 swrs 2CCC4 nop 1CCC2 ei 1CCC2 di 1CCC2 (20) special instructions: chkl, chkla mnemonic operands bytes clocks internal rom iram pram/emem/sfr others chkl sfr 3 C C 14 C chkla sfr 3 C C 14 C caution the chkl and chkla instructions are not available in the m pd784216, 784216y, 784218, 784218y, 784225, 784225y, 784937 subseries. do not execute these instructions. if these instructions are executed, the following operations will result. ? chkl instruction ....... after the pin levels of the output pins are read two times, they are exclusive-ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1). ? chkla instruction .... after the pin levels of output pins are read two times, they are exclusive- ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1) along with that the result is stored in the a register.
290 chapter 6 instruction set (21) string instructions: movtblw, movm, xchm, movbk, xchbk, cmpme, cmpmne, cmpmc, cmpmnc, cmpbke, cmpbkne, cmpbkc, cmpbknc mnemonic operands bytes clocks internal rom iram pram/emem/sfr others movtblw !addr16, byte 4 C 7 + 5n C C movm [tde +], a 2 C 3 + 8n 3 + 10n C [tde C], a 2 xchm [tde +], a 2 C 3 + 14n 3 + 20n C [tde C], a 2 movbk [tde +], [whl +] 2 3 + 17n note 1 3 + 13n note 2 3 + 17n note 3 C [tde C], [whl C] 2 xchbk [tde +], [whl +] 2 C 3 + 21n note 2 3 + 29n note 3 C [tde C], [whl C] 2 cmpme [tde +], a 2 3 + 12n 3 + 10n 3 + 12n C [tde C], a 2 cmpmne [tde +], a 2 3 + 12n 3 + 10n 3 + 12n C [tde C], a 2 cmpmc [tde +], a 2 3 + 12n 3 + 10n 3 + 12n C [tde C], a 2 cmpmnc [tde +], a 2 3 + 12n 3 + 10n 3 + 12n C [tde C], a 2 cmpbke [tde +], [whl +] 2 3 + 19n note 1 3 + 15n note 2 3 + 19n note 3 C [tde C], [whl C] 2 cmpbkne [tde +], [whl +] 2 3 + 19n note 1 3 + 15n note 2 3 + 19n note 3 C [tde C], [whl C] 2 cmpbkc [tde +], [whl +] 2 3 + 19n note 1 3 + 15n note 2 3 + 19n note 3 C [tde C], [whl C] 2 cmpbknc [tde +], [whl +] 2 3 + 19n note 1 3 + 15n note 2 3 + 19n note 3 C [tde C], [whl C] 2 notes 1. when the memory specified by the whl register is the internal rom and the memory specified by the tde register is pram or emem 2. if both the transfer source and destination memories are iram 3. if both the transfer source and destination memories are pram or emem
291 chapter 7 description of instructions this chapter describes the instructions of 78k/iv series products. each instruction is described on a mnemonic basis, with a number of operands covered together. the basic organization of the instruction descriptions is shown on the following page. refer to chapter 6 instruction set for the number of bytes in the instructions, and the operation codes.
292 chapter 7 description of instructions description example mnemonic full name move byte data transfer meaning of instruction [instruction format] mov dst, src : shows the basic description format of the instruction. [operation] dst src : shows the operation of the instruction using symbols. [operands] : shows the operands that can be specified in this instruction. see chapter 6 instruction set for an explanation of the operand symbols. mnemonic operands mnemonic operands mov r, #byte mov [saddrp], a saddr, #byte [%saddrg], a a, saddr2 mem, a saddr2, a a, r3 a, mem r3, a [flags] : shows the operation of flags changed by execution of the instruction. the operation symbols for each flag are shown in the legend below. s z ac p/v cy legend symbol meaning blank no change 0 cleared to 0 1 set to 1 set or cleared depending on result p p/v flag operates as parity flag v p/v flag operates as overflow flag r previously saved value is restored [description] : explains the detailed operation of the instruction. ? transfers the contents of the source operand (src) specified by the 2nd operand to the destination operand (dst) specified by the 1st operand. [coding example] mov a, #4dh ; transfers 4dh to a register ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ mov
293 chapter 7 description of instructions 7.1 8-bit data transfer instruction there is one 8-bit data transfer instruction, a follows: mov ... 294
294 chapter 7 description of instructions move byte data transfer [instruction format] mov dst, src [operation] dst src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) mov r, #byte mov r, !!addr24 saddr, #byte !!addr24, r sfr, #byte a, [saddrp] !addr16, #byte a, [%saddrg] !!addr24, #byte a, mem r, r [saddrp], a a, r [%saddrg], a a, saddr2 mem, a r, saddr pswl, #byte saddr2, a pswh, #byte saddr, r pswl, a a, sfr pswh, a r, sfr a, pswl sfr, a a, pswh sfr, r r3, #byte saddr, saddr a, r3 r, !addr16 r3, a !addr16, r [flags] in case of pswl, #byte and pswl, a operands in other cases s z ac p/v cy s z ac p/v cy mov
295 chapter 7 description of instructions [description] ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. ? no interrupts or macro service requests are acknowledged between a mov pswl, #byte instruction or mov pswl, a instruction and the following instruction. ? instructions with r3 (t, u, v, or w register) as an operand should only be used when the high-order 8-bit of the address are set when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. also, if possible, the program should be amended so that r3 need not be specified directly. [coding example] mov a, #4dh ; transfers 4dh to a register
296 chapter 7 description of instructions 7.2 16-bit data transfer instruction there is one 16-bit data transfer instruction, as follows: movw ... 297
297 chapter 7 description of instructions move word word data transfer [instruction format] movw dst, src [operation] dst src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) movw rp, #word movw sfrp, rp saddrp, #word saddrp, saddrp sfrp, #word rp, !addr16 !addr16, #word !addr16, rp !!addr24, #word rp, !!addr24 rp, rp !!addr24, rp ax, saddrp2 ax, [saddrp] rp, saddrp ax, [%saddrg] saddr2, ax ax, mem saddrp, rp [saddrp], ax ax, sfrp [%saddrg], ax rp, sfrp mem, ax sfrp, ax [flags] s z ac p/v cy [description] ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. ? the following caution should be noted if all the following conditions apply when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. movw
298 chapter 7 description of instructions [conditions] ? an instruction in which rp is specified as an operand is used . ? de, hl, vp, or up is actually written for rp . ? de, hl, vp, or up is used as an address pointer [caution] ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address pointer are coordinated with de, hl, vp, or up that indicates the low-order 16 bits, and if program amendment is possible, change the program so that a 24-bit manipulation instruction is used. [coding example] movw ax, [whl] ; transfers the contents of memory indicated by the whl register to the ax register
299 chapter 7 description of instructions 7.3 24-bit data transfer instruction there is one 24-bit data transfer instruction, as follows: movg ... 300
300 chapter 7 description of instructions move g note 24-bit data transfer [instruction format] movg dst, src note g is a character that indicates that 24-bit data is to be manipulated. [operation] dst src [operands] mnemonic operands (dst, src) movg rp, #imm24 rg, rg rg, !!addr24 !!addr24, rg rg, saddrg saddrg, rg whl, [%saddrg] [%saddrg], whl whl, mem1 mem1, whl [flags] s z ac p/v cy [description] ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. [coding example] movg vvp, sadg ; transfers the 24-bit data in address sadg that can be accessed by short direct addressing to the vvp register. movg
301 chapter 7 description of instructions 7.4 8-bit data exchange instruction there is one 8-bit data exchange instruction, as follows: xch ... 302
302 chapter 7 description of instructions exchange byte data exchange [instruction format] xch dst, src [operation] dst src [operands] mnemonic operands (dst, src) xch r, r a, r a, saddr2 r, saddr r, sfr saddr, saddr r, !addr16 r, !!addr24 a, [saddrp] a, [%saddrg] a, mem [flags] s z ac p/v cy [description] ? exchanges the contents of the 1st operand and 2nd operand. [coding example] xch b, d ; exchanges the contents of the b register with the contents of the d register xch
303 chapter 7 description of instructions 7.5 16-bit data exchange instruction there is one 16-bit data exchange instruction, as follows: xchw ... 304
304 chapter 7 description of instructions exchange word data exchange [instruction format] xchw dst, src [operation] dst src [operands] mnemonic operands (dst, src) xchw rp, rp ax, saddrp2 rp, saddrp rp, sfrp ax, [saddrp] ax, [%saddrg] ax, !addr16 ax, !!addr24 saddrp, saddrp ax, mem [flags] s z ac p/v cy [description] ? exchanges the contents of the 1st operand and 2nd operand. ? the following caution should be noted if all the following conditions apply when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. [conditions] ? an instruction in which rp is specified as an operand is used ? de, hl, vp, or up is actually written for rp ? de, hl, vp, or up is used as an address pointer [caution] ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address pointer are coordinated with de, hl, vp, or up that indicates the low-order 16 bits, and if program amendment is possible, change the program so that a 24-bit manipulation instruction is used. [coding example] xchw ax, mem ; exchanges the contents of the ax register with the memory contents addressed by memory addressing xchw
305 chapter 7 description of instructions 7.6 8-bit operation instructions 8-bit operation instructions are as follows: add ... 306 addc ... 307 sub ... 308 subc ... 309 cmp ... 310 and ... 312 or ... 313 xor ... 314
306 chapter 7 description of instructions add byte data addition [instruction format] add dst, src [operation] dst, cy dst + src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) add a, #byte add a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is added to the destination operand (dst) specified by the 1st operand, and the result is stored in the cy flag and destination operand (dst). ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the addition, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the addition, and cleared (0) otherwise. ? the ac flag is set (1) if a carry is generated out of bit 3 into bit 4 as a result of the addition, and cleared (0) otherwise. ? the p/v flag is set (1) if a carry is generated out of bit 6 into bit 7 and a carry is not generated out of bit 7 as a result of the addition (when overflow is generated by a twos complement type operation), or if a carry is not generated out of bit 6 into bit 7 and a carry is generated out of bit 7 (when underflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a carry is generated out of bit 7 as a result of the addition, and cleared (0) otherwise. [coding example] add cr11, #56h ; adds 56h to the value in register cr11, and stores the result in register cr11 add
307 chapter 7 description of instructions add with carry byte data addition including carry [instruction format] addc dst, src [operation] dst, cy dst + src + cy [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) addc a, #byte addc a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand and the cy flag are added to the destination operand (dst) specified by the 1st operand, and the result is stored in the destination operand (dst) and the cy flag. this instruction is mainly used when performing multiple byte addition. ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the addition, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the addition, and cleared (0) otherwise. ? the ac flag is set (1) if a carry is generated out of bit 3 into bit 4 as a result of the addition, and cleared (0) otherwise. ? the p/v flag is set (1) if a carry is generated out of bit 6 into bit 7 and a carry is not generated out of bit 7 as a result of the addition (when overflow is generated by a twos complement type operation), or if a carry is not generated out of bit 6 into bit 7 and a carry is generated out of bit 7 (when underflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a carry is generated out of bit 7 as a result of the addition, and cleared (0) otherwise. [coding example] addc a, 12345h [b] ; adds the contents of address (12345h + (b register)) and the cy flag to the a register, and stores the result in the a register addc
308 chapter 7 description of instructions subtract byte data subtraction [instruction format] sub dst, src [operation] dst, cy dst C src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) sub a, #byte sub a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand, and the result is stored in the destination operand (dst) and the cy flag. ? the destination operand (dst) can be cleared to 0 by making the source operand (src) and destination operand (dst) the same. ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated out of bit 6 into bit 7 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated out of bit 6 into bit 7 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. [coding example] sub d, l ; subtracts the l register from the d register and stores the result in the d register sub
309 chapter 7 description of instructions subtract with carry byte data subtraction including carry [instruction format] subc dst, src [operation] dst, cy dst C src C cy [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) subc a, #byte subc a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand and the cy flag are subtracted from the destination operand (dst) specified by the 1st operand, and the result is stored in the destination operand (dst) and the cy flag. the cy flag is subtracted from the lsb. this instruction is mainly used when performing multiple byte subtraction. ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated out of bit 6 into bit 7 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated out of bit 6 into bit 7 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. [coding example] subc a, [tde+] ; subtracts the contents of the tde register address and the cy flag from the a register, and stores the result in the a register (the tde register is incremented after the subtraction) subc
310 chapter 7 description of instructions compare byte data comparison [instruction format] cmp dst, src [operation] dst C src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) cmp a, #byte cmp a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand. the result of the subtraction is not stored anywhere, and only the s, z, ac, p/v, and cy flags are changed. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 7 and a borrow is not generated in bit 6 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 7 and a borrow is generated in bit 6 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmp
311 chapter 7 description of instructions [coding example] cmp sadg1, sadg2 ; subtracts the contents of address sadg2 that can be accessed by short direct addressing from the contents of address sadg1 that can be accessed by short direct addressing, and changes the flags only (comparison of the contents of address sadg1 and the contents of address sadg2)
312 chapter 7 description of instructions and byte data logical product [instruction format] and dst, src [operation] dst dst src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) and a, #byte and a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy p [description] ? the bit-wise logical sum of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is found, and the result is stored in the destination operand (dst). ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the logical product operation, and cleared (0) otherwise. ? the z flag is set (1) if all bits are 0 as a result of the logical product operation, and cleared (0) otherwise. ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the logical product operation is even, and cleared (0) otherwise. [coding example] and sadg, #11011100b ; finds the bit-wise logical product of the contents of address sadg that can be accessed by short direct addressing and 11011100b, and stores the result in sadg and
313 chapter 7 description of instructions or byte data logical sum [instruction format] or dst, src [operation] dst dst src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) or a, #byte or a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy p [description] ? the bit-wise logical sum of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is found, and the result is stored in the destination operand (dst). ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the logical sum operation, and cleared (0) otherwise. ? the z flag is set (1) if all bits are 0 as a result of the logical sum operation, and cleared (0) otherwise. ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the logical sum operation is even, and cleared (0) otherwise. [coding example] or a, !!12345h ; finds the bit-wise logical sum of the contents of the a register and address 12345h, and stores the result in the a register or
314 chapter 7 description of instructions exclusive or byte data exclusive logical sum [instruction format] xor dst, src [operation] dst dst src [operands] mnemonic operands (dst, src) mnemonic operands (dst, src) xor a, #byte xor a, [saddrp] r, #byte a, [%saddrg] saddr, #byte [saddrp], a sfr, #byte [%saddrg], a r, r a, !addr16 a, saddr2 a, !!addr24 r, saddr !addr16, a saddr, r !!addr24, a r, sfr a, mem sfr, r mem, a saddr, saddr [flags] s z ac p/v cy p [description] ? the bit-wise exclusive logical sum of the destination operand (dst) specified by the 1st operand and the source operand (src) specified by the 2nd operand is found, and the result is stored in the destination operand (dst). ? selecting #0ffh as the source operand (src) in this instruction results in logical negation of all the bits of the destination operand (dst). ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the exclusive logical sum operation, and cleared (0) otherwise. ? the z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and cleared (0) otherwise. ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the exclusive logical sum operation is even, and cleared (0) otherwise. [coding example] xor c, p2 ; finds the bit-wise exclusive logical sum of the c register and p2 register, and stores the result in the c register xor
315 chapter 7 description of instructions 7.7 16-bit operation instructions 16-bit operation instructions are as follows: addw ... 316 subw ... 318 cmpw ... 320
316 chapter 7 description of instructions add word word data addition [instruction format] addw dst, src [operation] dst, cy dst + src [operands] mnemonic operands (dst, src) addw ax, #word rp, #word rp, rp ax, saddrp2 rp, saddrp saddrp, rp rp, sfrp sfrp, rp saddrp, #word sfrp, #word saddrp, saddrp [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is added to the destination operand (dst) specified by the 1st operand, and the result is stored in the destination operand (dst). ? the s flag is set (1) if bit 15 of dst is set (1) as a result of the addition, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the addition, and cleared (0) otherwise. ? the ac flag is undefined as a result of the addition. ? the p/v flag is set (1) if a carry is generated out of bit 14 into bit 15 and a carry is not generated out of bit 15 as a result of the addition (when overflow is generated by a twos complement type operation), or if a carry is not generated out of bit 14 into bit 15 and a carry is generated out of bit 15 (when underflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a carry is generated out of bit 15 as a result of the addition, and cleared (0) otherwise. ? the following caution should be noted if all the following conditions apply when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. addw
317 chapter 7 description of instructions [conditions] ? an instruction in which rp is specified as an operand is used ? de, hl, vp, or up is actually written for rp ? de, hl, vp, or up is used as an address pointer [caution] ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address pointer are coordinated with de, hl, vp, or up that indicates the low-order 16 bits, and if program amendment is possible, change the program so that a 24-bit manipulation instruction is used. [coding example] addw bc, #0abcdh ; adds 0abcdh to the bc register, and stores the result in the bc register
318 chapter 7 description of instructions subtract word word data subtraction [instruction format] subw dst, src [operation] dst, cy dst C src [operands] mnemonic operands (dst, src) subw ax, #word rp, #word rp, rp ax, saddrp2 rp, saddrp saddrp, rp rp, sfrp sfrp, rp saddrp, #word sfrp, #word saddrp, saddrp [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand, and the result is stored in the destination operand (dst) and the cy flag. ? the destination operand (dst) can be cleared to 0 by making the source operand (src) and destination operand (dst) the same. ? the s flag is set (1) if bit 15 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise. ? the ac flag is undefined as a result of the subtraction. ? the p/v flag is set (1) if a borrow is generated out of bit 14 into bit 15 and a borrow is not generated in bit 15 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated out of bit 14 into bit 15 and a borrow is generated in bit 15 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 15 as a result of the subtraction, and cleared (0) otherwise. ? the following caution should be noted if all the following conditions apply when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. subw
319 chapter 7 description of instructions [conditions] ? an instruction in which rp is specified as an operand is used ? de, hl, vp, or up is actually written for rp ? de, hl, vp, or up is used as an address pointer [caution] ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address pointer are coordinated with de, hl, vp, or up that indicates the low-order 16 bits, and if program amendment is possible, change the program so that a 24-bit manipulation instruction is used. [coding example] subw cr01, ax ; subtracts the contents of the ax register from the contents of the cr01 register and stores the result in the cr01 register
320 chapter 7 description of instructions compare word word data comparison [instruction format] cmpw dst, src [operation] dst C src [operands] mnemonic operands (dst, src) cmpw ax, #word rp, #word rp, rp ax, saddrp2 rp, saddrp saddrp, rp rp, sfrp sfrp, rp saddrp, #word sfrp, #word saddrp, saddrp [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand. the result of the subtraction is not stored anywhere, and only the z, ac, and cy flags are changed. ? the s flag is set (1) if bit 15 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if dst is 0 as a result of the subtraction, and cleared (0) otherwise. ? the ac flag is undefined as a result of the subtraction. ? the p/v flag is set (1) if a borrow is generated out of bit 14 into bit 15 and a borrow is not generated in bit 15 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated out of bit 14 into bit 15 and a borrow is generated in bit 15 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 15 as a result of the subtraction, and cleared (0) otherwise. ? the following caution should be noted if all the following conditions apply when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. cmpw
321 chapter 7 description of instructions [conditions] ? an instruction in which rp is specified as an operand is used ? de, hl, vp, or up is actually written for rp ? de, hl, vp, or up is used as an address pointer [caution] ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address pointer are coordinated with de, hl, vp, or up that indicates the low-order 16 bits, and if program amendment is possible, change the program so that a 24-bit manipulation instruction is used. [coding example] cmpw ax, sadg ; subtracts the word data in address sadg that can be accessed by short direct addressing from the ax register, and changes the flags only (comparison of ax register and address sadg word data)
322 chapter 7 description of instructions 7.8 24-bit operation instructions 24-bit operation instructions are as follows: addg ... 323 subg ... 324
323 chapter 7 description of instructions add g note 24-bit data addition [instruction format] addg dst, src note g is a character that indicates that 24-bit data is to be manipulated. [operation] dst dst + src [operands] mnemonic operands (dst, src) addg rg, rg rg, #imm24 whl, saddrg [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is added to the destination operand (dst) specified by the 1st operand. the result of the addition is stored in dst, and the s, z, ac, p/v, and cy flags are changed. ? the s flag is set (1) if bit 23 of dst is set (1) as a result of the addition, and cleared (0) otherwise. ? the z flag is set (1) if the result of the addition is 0, and cleared (0) otherwise. ? the ac flag is undefined as a result of the addition. ? the p/v flag is set (1) if a carry is generated out of bit 22 into bit 23 and a carry is not generated out of bit 23 as a result of the addition (when overflow is generated by a twos complement type operation), or if a carry is not generated out of bit 22 into bit 23 and a carry is generated out of bit 23 (when underflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a carry is generated out of bit 23 as a result of the addition, and cleared (0) otherwise. [coding example] addg tde, vvp ; adds the vvp register to the tde register, and stores the result in the tde register addg
324 chapter 7 description of instructions subtract g note 24-bit data subtraction [instruction format] subg dst, src note g is a character that indicates that 24-bit data is to be manipulated. [operation] dst dst C src [operands] mnemonic operands (dst, src) subg rg, rg rg, #imm24 whl, saddrg [flags] s z ac p/v cy v [description] ? the source operand (src) specified by the 2nd operand is subtracted from the destination operand (dst) specified by the 1st operand. the result of the subtraction is stored in dst, and the s, z, ac, p/v, and cy flags are changed. ? the s flag is set (1) if bit 23 of dst is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and cleared (0) otherwise. ? the ac flag is undefined as a result of the subtraction. ? the p/v flag is set (1) if a borrow is generated out of bit 23 into bit 22 and a borrow is not generated in bit 23 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated out of bit 23 into bit 22 and a borrow is generated in bit 23 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 23 as a result of the subtraction, and cleared (0) otherwise. [coding example] subg uup, #543210h ; subtracts 543210h from the contents of the uup register and stores the result in the uup register subg
325 chapter 7 description of instructions 7.9 multiplication/division instructions multiplication/division instructions are as follows: mulu ... 326 muluw ... 327 mulw ... 328 divuw ... 329 divux ... 330
326 chapter 7 description of instructions multiply unsigned unsigned data multiplication [instruction format] mulu src [operation] ax a src [operands] mnemonic operands (src) mulu r [flags] s z ac p/v cy [description] ? the contents of the a register and the source operand (src) data are multiplied as unsigned data, and the result is stored in the ax register. [coding example] mulu h ; multiplies the contents of the a register by the contents of the h register, and stores the result in the ax register mulu
327 chapter 7 description of instructions multiply unsigned word unsigned word data multiplication [instruction format] muluw src [operation] ax (upper half), src (lower half) ax src [operands] mnemonic operands (src) muluw rp [flags] s z ac p/v cy [description] ? the contents of the ax register and the source operand (src) data are multiplied as unsigned data, and the high- order 16 bits of the result are stored in the ax register, and the low-order 16 bits in the source operand. ? when the ax register is specified as the source operand (src), the high-order 16 bits of the multiplied result are stored in the ax register, and the low-order 16 bits are not stored anywhere. [coding example] muluw hl ; multiplies the contents of the ax register by the contents of the hl register, and stores the result in the ax register and hl register muluw
328 chapter 7 description of instructions multiply signed word signed word data multiplication [instruction format] mulw src [operation] ax (upper half), src (lower half) ax src [operands] mnemonic operands (src) mulw rp [flags] s z ac p/v cy [description] ? the contents of the ax register and the source operand (src) data are multiplied as signed data, and the high- order 16 bits of the result are stored in the ax register, and the low-order 16 bits in the source operand. ? when the ax register is specified as the source operand (src), the high-order 16 bits of the multiplied result are stored in the ax register, and the low-order 16 bits are not stored anywhere. [coding example] mulw hl ; multiplies the contents of the ax register by the contents of the hl register, and stores the result in the ax register and hl register mulw
329 chapter 7 description of instructions divide unsigned word unsigned word data division [instruction format] divuw dst [operation] ax (quotient), dst (remainder) ax dst [operands] mnemonic operands (dst) divuw r [flags] s z ac p/v cy [description] ? the contents of the ax register are divided by the contents of the destination operand (dst), and the quotient is stored in the ax register, and the remainder in the destination operand (dst). the division is performed with the ax register and destination operand (dst) contents as unsigned data. ? if division by 0 is performed, the following will result: C ax (quotient) = ffffh C dst (remainder) = original x register value ? when the a register is specified as the destination operand (dst), the remainder is stored in the a register, and the low-order 8 bits of the quotient are stored in the x register. ? when the x register is specified as the destination operand (dst), the high-order 8 bits of the quotient are stored in the a register, and the remainder is stored in the x register. [coding example] divuw e ; divides the contents of the ax register by the contents of the e register, and stores the quotient in the ax register and the remainder in the e register divuw
330 chapter 7 description of instructions divide unsigned word expansion word unsigned doubleword data division [instruction format] divux dst [operation] axde (quotient), dst (remainder) axde dst [operands] mnemonic operands (dst) divux rp [flags] s z ac p/v cy [description] ? 32-bit data with the contents of the ax register as the high-order 16 bits and the contents of the de register as the low-order 16 bits is divided by the contents of the destination operand (dst), the high-order 16 bits of the quotient are stored in the ax register, the low-order 16 bits in the de register, and the remainder in the destination operand (dst). the division is performed with the contents of the 32-bit data indicated by the ax register and de register and the contents of the destination operand (dst) as unsigned data. ? if division by 0 is performed, the following will result: C axde (quotient) = ffffffffh C dst (remainder) = original de register value ? when the ax register is specified as the destination operand (dst), the remainder is stored in the ax register, and the low-order 16 bits of the quotient are stored in the de register. ? when the de register is specified as the destination operand (dst), the high-order 8 bits of the quotient is stored in the ax register, and the remainder is stored in the de register. [coding example] divux bc ; divides the contents of the axde register by the contents of the bc register, and stores the high- order 16 bits of the quotient in the ax register, the low-order 16 bits in the de register, and the remainder in the bc register divux
331 chapter 7 description of instructions 7.10 special operation instructions special operation instructions are as follows: macw ... 332 macsw ... 335 sacw ... 338
332 chapter 7 description of instructions multiply and accumulate word word data sum of products operation [instruction format] macw dst [operation] axde (b) (c) + axde, b b + 2, c c + 2, byte byte C 1 end if (byte = 0 or p/v = 1) [operands] mnemonic operands (dst, src) macw byte [flags] s z ac p/v cy v [description] ? signed multiplication is performed of the contents of the 2-byte area addressed by the b register and the contents of the 2-byte area addressed by the c register, and binary addition is performed of the result and the contents of the axde register. ? after the result of the addition is stored in the axde register, the contents of the b register and c register are incremented by 2. ? the above operations are repeated the number of times equal to the 8-bit immediate data written in the operand. ? if overflow or underflow is generated as a result of the addition, the value of the axde register is undefined. also, the b register and c register keep their values prior to overflow. ? the area addressed by the macw instruction is limited to addresses 0fe00h to 0feffh when the location 0 instruction is executed, or addresses 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the lower byte of the address is specified by the b register and c register. addresses fe80h to feffh (ffe80h to ffeffh when the location 0fh instruction is executed) are also used as general registers. ? interrupts and macro service requests are not acknowledged during execution of the macw instruction. ? the macw instruction does not clear the value of the axde register pair automatically, and therefore this should be cleared by the program if necessary. ? the s, z, ac, and cy flags are undefined as a result of the operation. ? the p/v flag is set (1) if overflow or underflow occurs, and cleared (0) otherwise. macw
333 chapter 7 description of instructions note when a location 0 instruction is executed. 0ffe00h when a location 0fh instruction is executed. the m pd784915 subseries is fixed to the location 0 instruction. byte word 0fe00h note + (c register) byte word 0fe00h note + (b register) 15 0 + 31 0 axde p/v set (1) in case of overflow or underflow. calculation is suspended when p/v is set to 1.
334 chapter 7 description of instructions [coding example] macw 5 ; executes sum of products operation 5 times macw axde axde + (data addressed by b register) (data addressed by c register) overflow or underflow generated? end yes no no yes byte = 0? b b + 2 c c + 2 byte byte ?1
335 chapter 7 description of instructions multiply and accumulate with saturation word sum of products operation with saturation function [instruction format] macsw byte [operation] axde (b) (c) + axde, b b + 2, c c + 2, byte byte C 1 if byte = 0 then end, if p/v = 1, then if overflow axde 7fffffffh, end, if underflow axde 80000000h, end [operands] mnemonic operands ($addr16) macsw byte [flags] s z ac p/v cy v [description] ? signed multiplication is performed of the contents of the 2-byte area addressed by the b register and the contents of the 2-byte area addressed by the c register, and binary addition is performed of the result and the contents of the axde register. ? after the result of the addition is stored in the axde register, the contents of the b register and c register are incremented by 2. ? the above operations are repeated the number of times equal to the 8-bit immediate data written in the operand. ? if overflow is generated as a result of the addition, the p/v flag is set (1) and the value of the axde register is 7fffffffh. if underflow is generated, the p/v flag is set (1) and the axde register value is 80000000h. the b register and c register keep their values prior to overflow or underflow. ? the area addressed by the macsw instruction is limited to addresses 0fe00h to 0feffh when the location 0 instruction is executed, or addresses 0ffe00h to 0ffeffh when the location 0fh instruction is executed. the lower byte of the address is specified by the b register and c register. addresses fe80h to feffh (ffe80h to ffeffh when the location 0fh instruction is executed) are also used as general registers. ? interrupts and macro service requests are not acknowledged during execution of the macsw instruction. ? the macsw instruction does not clear the value of the axde register pair automatically, and therefore this should be cleared by the program if necessary. ? the s, z, ac, and cy flags are undefined as a result of the operation. ? the p/v flag is set (1) if overflow or underflow occurs, and cleared (0) otherwise. macsw
336 chapter 7 description of instructions note when a location 0 instruction is executed. 0ffe00h when a location 0fh instruction is executed. the m pd784915 subseries is fixed to the location 0 instruction. byte word 0fe00h note + (c register) byte word 0fe00h note + (b register) 15 0 + 31 0 axde p/v set (1) in case of overflow or underflow. when p/v is set to 1. calculation is suspended, and 7fffffffh (in case of overflow) or 80000000h (in case of underflow) is loaded into axde.
337 chapter 7 description of instructions [coding example] macsw 6 ; executes sum of products operation 6 times macsw axde axde + (data addressed by b register) (data addressed by c register) overflow or underflow generated? end yes no no yes no byte = 0? overflow? axde 7fffffffh b b + 2 c c + 2 byte byte ?1 yes axde 80000000h
338 chapter 7 description of instructions subtract, absolute and accumulate word correlation instruction [instruction format] sacw [tde +], [whl +] [operation] ax | (tde) C (whl) | + ax, tde tde + 2, whl whl + 2, c c C 1, end if (c = 0 or cy = 1) [operands] mnemonic operands ($addr16) sacw [tde +], [whl +] [flags] s z ac p/v cy [description] ? subtraction is performed on the 16-bit data items addressed by the tde register and whl register, the absolute value of the result is added to the contents of the ax register, and the result is stored in the ax register. ? each time the above operation is performed, the contents of the tde and whl registers are incremented by 2, and the contents of the c register are decremented by 1. ? the above operations are repeated until the c register value is 0 or a carry is generated out of bit 15 as a result of the addition. ? if a carry occurs from bit 15 as a result of addition, therefore stopping repetition, the tde and whl registers retain the values immediately before the carry has occurred plus 2. the c register retains the value immediately before the carry has occurred. ? if an interrupt or macro service request that can be acknowledged during execution of the sacw instruction is generated, the interrupt or macro service processing is performed before the series of operation processing. when an interrupt is acknowledged, the program counter (pc) value saved to the stack is the sacw instruction start address. therefore, after returning from the interrupt, continuation of the interrupted sacw instruction is executed. ? the cy flag is set (1) if a carry is generated out of bit 15 as a result of the final addition, and cleared (0) otherwise. ? the contents of the s, z, ac, and p/v flags are undefined. ? the sacw instruction does not clear the contents of the ax register pair automatically, and therefore this should be done by the program if necessary. sacw
339 chapter 7 description of instructions (c register word) (c register word) whl tde 15 0 + conversion to absolute value conversion to absolute value conversion to absolute value calculation is suspended when cy is set to 1. ax cy 15 0
340 chapter 7 description of instructions [coding example] sacw [tde+], [whl+] ; executes a correlation instruction sacw acknowledgeable interrupt or macro service request? yes no cy = 1 ax ax + ? (tde) ?(whl) ? tde tde + 2 whl whl + 2 end c c ?1 c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no no
341 chapter 7 description of instructions 7.11 increment/decrement instructions increment/decrement instructions are as follows: inc ... 342 dec ... 343 incw ... 344 decw ... 345 incg ... 346 decg ... 347
342 chapter 7 description of instructions increment byte data increment [instruction format] inc dst [operation] dst dst + 1 [operands] mnemonic operands (dst) inc r saddr [flags] s z ac p/v cy v [description] ? the contents of the destination operand (dst) are incremented by 1. ? the z flag is set (1) if the result of the increment is 0, and cleared (0) otherwise. ? the ac flag is set (1) if a carry is generated out of bit 3 into bit 4 as a result of the increment, and cleared (0) otherwise. ? the cy flag value does not change since this is often used for repeat processing counter or indexed address offset register incrementing (as the cy flag value is retained in a multiple-byte operation). ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the increment, and cleared (0) otherwise. ? the p/v flag is set (1) if a carry is generated out of bit 6 into bit 7 and a carry is not generated out of bit 7 as a result of the increment (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. [coding example] inc b ; increments the b register inc
343 chapter 7 description of instructions decrement byte data decrement [instruction format] dec dst [operation] dst dst C 1 [operands] mnemonic operands (dst) dec r saddr [flags] s z ac p/v cy v [description] ? the contents of the destination operand (dst) are decremented by 1. ? the z flag is set (1) if the result of the decrement is 0, and cleared (0) otherwise. ? the ac flag is set (1) if a carry is generated out of bit 4 into bit 3 as a result of the decrement, and cleared (0) otherwise. ? the cy flag value does not change since this is often used for repeat processing counter or indexed address offset register decrementing (as the cy flag value is retained in a multiple-byte operation). ? the s flag is set (1) if bit 7 of dst is set (1) as a result of the decrement, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated out of bit 6 into bit 7 and a borrow is not generated in bit 7 as a result of the decrement (when underflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? if dst is the b register, c register or saddr, and you do not want to change the s, z, ac, or p/v flag, the dbnz instruction can be used. [coding example] dec sad1 ; decrements the contents of address sad1 that can be accessed by short direct addressing dec
344 chapter 7 description of instructions increment word word data increment [instruction format] incw dst [operation] dst dst + 1 [operands] mnemonic operands (dst) incw rp saddrp [flags] s z ac p/v cy [description] ? the contents of the destination operand (dst) are incremented by 1. ? the s, z, ac, p/v, and cy flags are not changed since this is often used for incrementing the register used in addressing that uses a register. ? if the hl, de, vp, or up register (vp and up: 78k/iii series only) is used as the base register in register indirect addressing, base addressing or based index addressing (78k/0 and 78k/iii series only) when rp is specified as the operand and a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used, ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address are coordinated with the de, hl, vp, or up register that indicates the low-order 16 bits. also, if program amendment is possible, the program should be changed so that a 24-bit manipulation instruction (incg instruction) is used. [coding example] incw hl ; increments the hl register incw
345 chapter 7 description of instructions decrement word word data decrement [instruction format] decw dst [operation] dst dst C 1 [operands] mnemonic operands (dst) decw rp saddrp [flags] s z ac p/v cy [description] ? the contents of the destination operand (dst) are decremented by 1. ? the s, z, ac, p/v, and cy flags are not changed since this is often used for decrementing the register used in addressing that uses a register. ? if the hl, de, vp, or up register (vp and up: 78k/iii series only) is used as the base register in register indirect addressing, base addressing or based index addressing (78k/0 and 78k/iii series only) when rp is specified as the operand and a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used, ensure that the contents of the t, w, v, or u register that indicates the high-order 8 bits of the address are coordinated with the de, hl, vp, or up register that indicates the low-order 16 bits. also, if program amendment is possible, the program should be changed so that a 24-bit manipulation instruction (incg instruction) is used. [coding example] decw de ; decrements the de register decw
346 chapter 7 description of instructions increment g note 24-bit data increment [instruction format] incg dst note g is a character that indicates that 24-bit data is to be manipulated. [operation] dst dst + 1 [operands] mnemonic operands (dst) incg rg [flags] s z ac p/v cy [description] ? the contents of the destination operand (dst) are incremented by 1. ? the s, z, ac, p/v, and cy flags are not changed since this is often used to decrement the register (pointer) used in addressing that uses a register. [coding example] incg uup ; increments the uup register incg
347 chapter 7 description of instructions decrement g note 24-bit data decrement [instruction format] decg dst note g is a character that indicates that 24-bit data is to be manipulated. [operation] dst dst C 1 [operands] mnemonic operands (dst) decg rg sp [flags] s z ac p/v cy [description] ? the contents of the destination operand (dst) are decremented by 1. ? the s, z, ac, p/v, and cy flags are not changed since this is often used to decrement the register (pointer) used in addressing that uses a register. [coding example] decg vvp ; decrements the vvp register decg
348 chapter 7 description of instructions 7.12 adjustment instructions adjustment instructions are as follows. adjba ... 349 adjbs ... 350 cvtbw ... 351
349 chapter 7 description of instructions decimal adjust register for addition decimal adjustment of addition result [instruction format] adjba [operation] decimal adjust accumulator for addition [operands] none [flags] s z ac p/v cy p [description] ? decimal adjustment of the a register, cy flag and ac flag is performed from the a register, cy flag and ac flag contents. this instruction only performs a meaningful operation when the addition result is stored in the a register after bcd (binary-code decimal) data has been added (in other cases, a meaningless operation is performed). the adjustment method is shown in the table below. condition operation a 3C0 9a 7C4 9 and cy = 0 a a, cy 0, ac 0 ac = 0 a 7C4 10 or cy = 1 a a + 01100000b, cy 1, ac 0 a 3C0 10 a 7C4 < 9 and cy = 0 a a + 00000110b, cy 0, ac 1 ac = 0 a 7C4 9 or cy = 1 a a + 01100110b, cy 1, ac 1 ac = 1 a 7C4 9 and cy = 0 a a + 00000110b, cy 0, ac 1 a 7C4 10 or cy = 1 a a + 01100110b, cy 1, ac 1 ? the z flag is set (1) if the contents of the a register are 0 as a result of the adjustment, and cleared (0) otherwise. ? the s flag is set (1) if bit 7 of the a register is 1 as a result of the adjustment, and cleared (0) otherwise. ? the p/v flag is set (1) if the number of bits set (1) in the a register as a result of the adjustment is even, and cleared (0) otherwise. [coding example] adjba ; performs decimal adjustment of the contents of the a register adjba
350 chapter 7 description of instructions decimal adjust register for subtraction decimal adjustment of subtraction result [instruction format] adjbs [operation] decimal adjust accumulator for subtraction [operands] none [flags] s z ac p/v cy p [description] ? decimal adjustment of the a register, cy flag and ac flag is performed from the a register, cy flag and ac flag contents. this instruction only performs a meaningful operation when the subtraction result is stored in the a register after bcd (binary-code decimal) data has been subtracted (in other cases, a meaningless operation is performed). the adjustment method is shown in the table below. condition operation ac = 0 cy = 0 a a, cy 0, ac 0 cy = 1 a a C 01100000b, cy 1, ac 0 ac = 1 cy = 0 a a C 00000110b, cy 0, ac 1 cy = 1 a a C 01100110b, cy 1, ac 1 ? the z flag is set (1) if the contents of the a register are 0 as a result of the adjustment, and cleared (0) otherwise. ? the s flag is set (1) if bit 7 of the a register is 1 as a result of the adjustment, and cleared (0) otherwise. ? the p/v flag is set (1) if the number of bits set (1) in the a register as a result of the adjustment is even, and cleared (0) otherwise. [coding example] adjbs ; performs decimal adjustment of the contents of the a register adjbs
351 chapter 7 description of instructions convert byte to word conversion from byte data to word data [instruction format] cvtbw [operation] when a 7 = 0, x a, a 00h when a 7 = 1, x a, a ffh [operands] none [flags] s z ac p/v cy [description] ? the signed 8-bit data in the a register is extended to signed 16-bit data in the ax register. ? the s, z, ac, p/v, and cy flags are not changed by this instruction. [coding example] cvtbw ; extends the signed 8-bit data in the a register to signed 16-bit data and stores it in the ax register cvtbw
352 chapter 7 description of instructions 7.13 shift/rotate instructions shift/rotate instructions are as follows: ror ... 353 rol ... 354 rorc ... 355 rolc ... 356 shr ... 357 shl ... 358 shrw ... 359 shlw ... 360 ror4 ... 361 rol4 ... 362
353 chapter 7 description of instructions rotate right right rotation of byte data [instruction format] ror dst, cnt [operation] (cy, dst 7 dst 0 , dst mC1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) ror r, n [flags] s z ac p/v cy p [description] ? the contents of the destination operand (dst) specified by the 1st operand are rotated to the right cnt times specified by the 2nd operand. ? the contents of the lsb (bit 0) are rotated into the msb (bit 7) and are also transferred to the cy flag. ? if the 2nd operand (cnt) is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the right rotation is even, and cleared (0) otherwise. ? the s, z, and ac flags do not change irrespective of the result of the rotate operation. [coding example] ror r5, 4 ; rotates the contents of the r5 register 4 bits to the right ror cy 7 0
354 chapter 7 description of instructions rotate left left rotation of byte data [instruction format] rol dst, cnt [operation] (cy, dst 0 dst 7 , dst m+1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) rol r, n [flags] s z ac p/v cy p [description] ? the contents of the destination operand (dst) specified by the 1st operand are rotated to the left cnt times specified by the 2nd operand. ? the contents of the msb (bit 7) are rotated into the lsb (bit 0) and are also transferred to the cy flag. ? if the 2nd operand (cnt) is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the left rotation is even, and cleared (0) otherwise. ? the s, z, and ac flags do not change irrespective of the result of the rotate operation. [coding example] rol l, 2 ; rotates the contents of the l register 2 bits to the left rol cy 7 0
355 chapter 7 description of instructions rotate right with carry right rotation of byte data including carry [instruction format] rorc dst, cnt [operation] (cy dst 0 , dst 7 cy, dst mC1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) rorc r, n [flags] s z ac p/v cy p [description] ? the contents of the destination operand (dst) specified by the 1st operand, and the cy flag, are rotated to the right cnt times specified by the 2nd operand. ? if the 2nd operand (cnt) is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the right rotation is even, and cleared (0) otherwise. ? the s, z, and ac flags do not change irrespective of the result of the rotate operation. [coding example] rorc b, 1 ; rotates the contents of the b register and the cy flag 1 bit to the right rorc cy 7 0
356 chapter 7 description of instructions rotate left with carry left rotation of byte data including carry [instruction format] rolc dst, cnt [operation] (cy dst 7 , dst 0 cy, dst m+1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) rolc r, n [flags] s z ac p/v cy p [description] ? the contents of the destination operand (dst) specified by the 1st operand, and the cy flag, are rotated to the left cnt times specified by the 2nd operand. ? if the 2nd operand (cnt) is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? if you wish to perform a left rotation of 1 bit only, the execution time can be reduced by using addc r, r. ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the left rotation is even, and cleared (0) otherwise. ? the s, z, and ac flags do not change irrespective of the result of the rotate operation. [coding example] rolc r7, 3 ; rotates the contents of the r7 register and the cy flag 3 bits to the left rolc cy 7 0
357 chapter 7 description of instructions shift right (logical) logical right shift of byte data [instruction format] shr dst, cnt [operation] (cy dst 0 , dst 7 0, dst mC1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) shr r, n [flags] s z ac p/v cy 0p [description] ? the contents of the destination operand (dst) specified by the 1st operand are shifted to the right cnt times specified by the 2nd operand. 0 is shifted into the msb (bit 7) each time a 1-bit shift is performed. ? the s flag is cleared (0) if cnt is 1 or more. ? the z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise. ? the ac flag is always 0 irrespective of the result of the shift operation. ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the shift operation is even, and cleared (0) otherwise. ? the last data shifted out of the lsb (bit 0) as a result of the shift operation is set in the cy flag. ? if cnt is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? this instruction gives the same result as division of the destination operand (dst) as unsigned data by 2 cnt . [coding example] shr h, 2 ; shifts the contents of the h register 2 bits to the right shr cy 7 0 0
358 chapter 7 description of instructions shift left (logical) logical left shift of byte data [instruction format] shl dst, cnt [operation] (cy dst 7 , dst 0 0, dst m+1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) shl r, n [flags] s z ac p/v cy 0p [description] ? the contents of the destination operand (dst) specified by the 1st operand are shifted to the left cnt times specified by the 2nd operand. ? 0 is shifted into the lsb (bit 0) each time a 1-bit shift is performed. ? the s flag is set (1) if bit 7 of dst is 1 as a result of the shift operation, and cleared (0) if 0. ? the z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise. ? the ac flag is always 0 irrespective of the result of the shift operation. ? the p/v flag is set (1) if the number of bits set (1) in dst as a result of the shift operation is even, and cleared (0) otherwise. ? the last data shifted out of the lsb (bit 0) as a result of the shift operation is set in the cy flag. ? if cnt is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? if you wish to perform a left shift of 1 bit only, the execution time can be reduced by using add r, r. ? this instruction gives the same result as multiplication of the destination operand (dst) by 2 cnt (if the multiplication result is 8 bits or less). [coding example] shl e, 1 ; shifts the contents of the e register 1 bit to the left shl cy 7 0 0
359 chapter 7 description of instructions shift right (logical) word logical right shift of word data [instruction format] shrw dst, cnt [operation] (cy dst 0 , dst 15 0, dst mC1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) shrw rp, n [flags] s z ac p/v cy 0p [description] ? the contents of the destination operand (dst) specified by the 1st operand are shifted to the right cnt times specified by the 2nd operand. 0 is shifted into the msb (bit 15) each time a 1-bit shift is performed. ? the s flag is cleared (0) if cnt is 1 or more. ? the z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise. ? the ac flag is always 0 irrespective of the result of the shift operation. ? the p/v flag is set (1) if the number of bits set (1) in the low-order 8 bits of dst as a result of the shift operation is even, and cleared (0) otherwise. ? the last data shifted out of the lsb (bit 0) as a result of the shift operation is set in the cy flag. ? if cnt is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). ? this instruction gives the same result as division of the destination operand (dst) as unsigned data by 2 cnt . [coding example] shrw ax, 3 ; shifts the contents of the ax register 3 bits to the right (divides the contents of the ax register by 8) shrw cy 15 0 0
360 chapter 7 description of instructions shift left (logical) word logical left shift of word data [instruction format] shlw dst, cnt [operation] (cy dst 15 , dst 0 0, dst m+1 dst m ) cnt times cnt = 0 to 7 [operands] mnemonic operands (dst, cnt) shlw rp, n [flags] s z ac p/v cy 0p [description] ? the contents of the destination operand (dst) specified by the 1st operand are shifted to the right cnt times specified by the 2nd operand. ? 0 is shifted into the lsb (bit 0) each time a 1-bit shift is performed. ? the s flag is set (1) if bit 15 of dst is 1 as a result of the shift operation, and cleared (0) if 0. ? the z flag is set (1) if the result of the shift operation is 0, and cleared (0) otherwise. ? the ac flag is always 0 irrespective of the result of the shift operation. ? the p/v flag is set (1) if the number of bits set (1) in the low-order 8 bits of dst as a result of the shift operation is even, and cleared (0) otherwise. ? the last data shifted out of the lsb (bit 0) as a result of the shift operation is set in the cy flag. ? if cnt is 0, no processing is performed (and the s, z, ac, p/v, and cy flags do not change). [coding example] shlw e, 1 ; shifts the contents of the e register 1 bit to the left shlw cy 15 0 0
361 chapter 7 description of instructions rotate right digit right digit rotation [instruction format] ror4 dst [operation] a 3C0 (dst) 3C0 , (dst) 7C4 a 3C0 , (dst) 3C0 dst 7C4 [operands] mnemonic operands (dst) ror4 mem3 [flags] s z ac p/v cy [description] ? the low-order 4 bits of the a register and the two items of digit data (4-bit data) of the destination operand (dst) are rotated to the right. the high-order 4 bits of the a register are not changed. [coding example] ror4 [whl] ; performs digit rotation to the right of the a register and memory contents specified by the whl register. a (whl) 7430 7430 before execution 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 after execution 1 0 1 0 0 1 0 1 0 0 1 1 1 1 0 0 ror4 7430 a 7430 dst
362 chapter 7 description of instructions rotate left digit left digit rotation [instruction format] rol4 dst [operation] a 3C0 (dst) 7C4 , (dst) 3C0 a 3C0 , (dst) 7C4 dst 3C0 [operands] mnemonic operands (dst) rol4 mem3 [flags] s z ac p/v cy [description] ? the low-order 4 bits of the a register and the two items of digit data (4-bit data) of the destination operand (dst) are rotated to the left. the high-order 4 bits of the a register are not changed. [coding example] rol4 [tde] ; performs digit rotation to the left of the a register and memory contents specified by the tde register. a (tde) 7430 7430 before execution 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 after execution 0 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 rol4 7430 a 7430 dst
363 chapter 7 description of instructions 7.14 bit manipulation instructions bit manipulation instructions are as follows: mov1 ... 364 and1 ... 366 or1 ... 368 xor1 ... 370 not1 ... 371 set1 ... 372 clr1 ... 373
364 chapter 7 description of instructions move single bit 1-bit data transfer [instruction format] mov1 dst, src [operation] dst src [operands] mnemonic operands (dst, src) mov1 cy, saddr.bit cy, sfr.bit cy, x.bit cy, a.bit cy, pswl.bit cy, pswh.bit cy, mem2.bit cy, !addr16.bit cy, !!addr24.bit saddr.bit, cy sfr.bit, cy x.bit, cy a.bit, cy pswl.bit, cy pswh.bit, cy mem2.bit, cy !addr16.bit, cy !!addr24.bit, cy [flags] dst is pswl.bit dst is cy s z ac p/v cy s z ac p/v cy other cases s z ac p/v cy mov1
365 chapter 7 description of instructions [description] ? the source operand (src) bit data specified by the 2nd operand is transferred to the destination operand (dst) specified by the 1st operand. ? if the destination operand (dst) is cy or psw.bit, only the relevant flag changes. [coding example] mov1 p3.4, cy ; transfers the contents of the cy flag to bit 4 of port 3
366 chapter 7 description of instructions and single bit 1-bit data logical product [instruction format] and1 dst, src and1 dst, /src [operation] dst dst src dst dst src [operands] mnemonic operands (dst, src) and1 cy, saddr.bit cy, /saddr.bit cy, sfr.bit cy, /sfr.bit cy, x.bit cy, /x.bit cy, a.bit cy, /a.bit cy, pswl.bit cy, /pswl.bit cy, pswh.bit cy, /pswh.bit cy, mem2.bit cy, /mem2.bit cy, !addr16.bit cy, /!addr16.bit cy, !!addr24.bit cy, /!!addr24.bit [flags] s z ac p/v cy and1
367 chapter 7 description of instructions [description] ? the logical product of the destination operand (dst) specified by the 1st operand and the source operand (src) bit data specified by the 2nd operand is found, and the result is stored in the destination operand (dst). ? if the 2nd operand is immediately preceded by /, the logical product operation is performed on the logical not of the source operand (src). ? the cy flag stores the operation result (as it is the destination operand (dst)). [coding examples] and1 cy, sadr.3 ; finds the logical product of bit 3 of address sadr which can be accessed by short direct addressing and the cy flag, and stores the result in the cy flag and1 cy, /psw.6 ; finds the logical product of the logical not of bit 6 of the psw (z flag) and the cy flag, and stores the result in the cy flag
368 chapter 7 description of instructions or single bit 1-bit data logical sum [instruction format] or1 dst, src or1 dst, /src [operation] dst dst src dst dst src [operands] mnemonic operands (dst, src) or1 cy, saddr.bit cy, /saddr.bit cy, sfr.bit cy, /sfr.bit cy, x.bit cy, /x.bit cy, a.bit cy, /a.bit cy, pswl.bit cy, /pswl.bit cy, pswh.bit cy, /pswh.bit cy, mem2.bit cy, /mem2.bit cy, !addr16.bit cy, /!addr16.bit cy, !!addr24.bit cy, /!!addr24.bit [flags] s z ac p/v cy or1
369 chapter 7 description of instructions [description] ? the logical sum of the destination operand (dst) specified by the 1st operand and the source operand (src) bit data specified by the 2nd operand is found, and the result is stored in the destination operand (dst). ? if the 2nd operand is immediately preceded by /, the logical sum operation is performed on the logical not of the source operand (src). ? the cy flag stores the operation result (as it is the destination operand (dst)). [coding examples] or1 cy, p2.5; finds the logical sum of bit 5 of port 2 and the cy flag, and stores the result in the cy flag or1 cy, /x.0 ; finds the logical sum of the logical not of bit 0 of the x register and the cy flag, and stores the result in the cy flag
370 chapter 7 description of instructions exclusive or single bit 1-bit data exclusive logical sum [instruction format] xor1 dst, src [operation] dst dst src [operands] mnemonic operands (dst, src) xor1 cy, saddr.bit cy, sfr.bit cy, x.bit cy, a.bit cy, pswl.bit cy, pswh.bit cy, mem2.bit cy, !addr16.bit cy, !!addr24.bit [flags] s z ac p/v cy [description] ? the exclusive logical sum of the destination operand (dst) specified by the 1st operand and the source operand (src) bit data specified by the 2nd operand is found, and the result is stored in the destination operand (dst). ? the cy flag stores the operation result (as it is the destination operand (dst)). [coding example] xor1 cy, a.7 ; finds the exclusive logical sum of bit 7 of the a register and the cy flag, and stores the result in the cy flag xor1
371 chapter 7 description of instructions not single bit (carry flag) 1-bit data logical not [instruction format] not1 dst [operation] dst dst [operands] mnemonic operands (dst) not1 saddr.bit sfr.bit x.bit a.bit pswl.bit pswh.bit mem2.bit !addr16.bit !!addr24.bit cy [flags] dst is pswl.bit dst is cy s z ac p/v cy s z ac p/v cy other cases s z ac p/v cy [description] ? the logical not of the bit specified by the destination operand (dst) is found, and the result is stored in the destination operand (dst). ? if the destination operand (dst) is cy or psw.bit, only the relevant flag changes. [coding examples] not1 a.2 ; inverts bit 2 of the a register not1
372 chapter 7 description of instructions set single bit (carry flag) 1-bit data setting [instruction format] set1 dst [operation] dst 1 [operands] mnemonic operands (dst) set1 saddr.bit sfr.bit x.bit a.bit pswl.bit pswh.bit mem2.bit !addr16.bit !!addr24.bit cy [flags] dst is pswl.bit dst is cy s z ac p/v cy s z ac p/v cy 1 other cases s z ac p/v cy [description] ? the destination operand (dst) is set (1). ? if the destination operand (dst) is cy or psw.bit, only the relevant flag is set (1). [coding example] set1 bitsym ; sets (1) the contents of a bit located in an area that can be accessed by short direct addressing set1
373 chapter 7 description of instructions clear single bit (carry flag) 1-bit data clear [instruction format] clr1 dst [operation] dst 0 [operands] mnemonic operands (dst) clr1 saddr.bit sfr.bit x.bit a.bit pswl.bit pswh.bit mem2.bit !addr16.bit !!addr24.bit cy [flags] dst is pswl.bit dst is cy s z ac p/v cy s z ac p/v cy 0 other cases s z ac p/v cy [description] ? the destination operand (dst) is cleared (0). ? if the destination operand (dst) is cy or psw.bit, only the relevant flag is cleared (0). [coding example] clr1 p3.7 ; clears (0) bit 7 of port 3 clr1
374 chapter 7 description of instructions 7.15 stack manipulation instructions stack manipulation instructions are as follows: push ... 375 pushu ... 377 pop ... 378 popu ... 380 movg ... 381 addwg ... 382 subwg ... 383 incg sp ... 384 decg sp ... 385
375 chapter 7 description of instructions push push [instruction format] push src [operation] note (1) when src is psw, sfrp (sp C 2) src, sp sp C 2 (2) when src is sfr (sp C 1) src, sp sp C 1 (3) when src is rg (sp C 3) src, sp sp C 3 (4) when src is post {(sp C 2) post, sp sp C 2} n times note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] mnemonic operands (src) push psw sfrp sfr post rg [flags] s z ac p/v cy push
376 chapter 7 description of instructions [description] ? the data in the registers specified by the source operand (src) is saved to the stack. ? if post is specified as the source operand, any combination of the following registers can be saved to the stack by the instruction. ax (rp0), bc (rp1), rp2, rp3, up, vp, de, hl the save order at this time is from the rightmost of the above registers. ? the vp, up, de, and hl registers should only be used when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. in other cases, saving to the stack should be specified individually as the uup, vvp, tde, and whl registers. moreover, saving to the stack should also be specified individually as the uup, vvp, tde, and whl registers when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. ? after the source operand (src) save, the stack pointer (sp) is decremented by the number of bytes of data saved. [coding example] push ax, bc, rp2, rp3 ; saves the contents of the ax, bc, rp2, and rp3 registers to the stack
377 chapter 7 description of instructions push to user stack register push to user stack [instruction format] pushu src [operation] note {(uup C 1) post, uup uup C 2} n times (n = number of register pairs written as post) note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] mnemonic operands (src) pushu post [flags] s z ac p/v cy [description] ? the contents of the 16-bit register pair specified by the source operand (src) are saved to the memory addressed by the user stack pointer (uup), and then the uup is decremented. ? any combination of the following registers can be written in post as the source operand (src). ax (rp0), bc (rp1), rp2, rp3, vp, psw, de, hl the save order at this time is from the rightmost of the above registers. [coding example] pushu bc, psw ; saves the contents of the bc register and psw to the stack pushu
378 chapter 7 description of instructions pop pop [instruction format] pop dst [operation] note (1) when dst is psw, sfrp dst (sp) sp sp + 2 (2) when dst is sfr dst (sp), sp sp + 1 (3) when dst is rg dst (sp), sp sp + 3 (4) when dst is post {post (sp), sp sp+2} n times note for details, refer to chapter 3, figure 3-4 data saved to stack area, and figure 3-5 data restored from stack area. [operands] mnemonic operands (dst) pop psw sfrp sfr post rg [flags] dst is psw in other cases s z ac p/v cy s z ac p/v cy rr r r r pop
379 chapter 7 description of instructions [description] ? data is restored from the stack to the registers specified by the destination operand (dst). ? if the destination operand (dst) is the psw, each flag is replaced with stack data. ? if post is specified as the destination operand (dst), data can be restored to any combination of the following registers by one instruction. ax (rp0), bc (rp1), rp2, rp3, vp (rp4), up (rp5), de (rp6), hl (rp7) the restoration order at this time is from the leftmost of the above registers. ? the up, vp, de, and hl registers should only be used when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. in other cases, restoration from the stack should be specified individually as the uup, vvp, tde, and whl registers. moreover, saving to the stack should also be specified individually as the uup, vvp, tde, and whl registers when a 78k/0, 78k/i, 78k/ii, or 78k/iii series program is used. ? after data has been restored from the stack, the stack pointer (sp) is incremented by the number of bytes of data restored. [coding example] pop imk0l ; restores stack data to the imk0l register
380 chapter 7 description of instructions pop from user stack register pop from user stack [instruction format] popu dst [operation] note {post (uup), uup uup + 2} n times (n = number of register pairs written as post) note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] mnemonic operands (dst) popu post [flags] s z ac p/v cy [description] ? the contents of the memory (stack) addressed by the user stack pointer (uup) are restored to the registers specified by the destination operand (dst), and then the uup is incremented. ? any combination of the following registers can be written in post as the destination operand (dst). ax (rp0), bc (rp1), rp2, rp3, vp (rp4), psw, de (rp6), hl (rp7) the restoration order at this time is from the leftmost of the above registers. [coding example] popu ax, bc ; restores stack data to the ax and bc registers popu
381 chapter 7 description of instructions move g note 24-bit data transfer [instruction format] movg dst, src note g is a character that indicates that 24-bit data is to be manipulated. [operation] when dst is sp when dst is whl sp src whl sp [operands] mnemonic operands (dst, src) movg sp, #imm24 sp, whl whl, sp [flags] s z ac p/v cy [description] ? the contents of the source operand (src) specified by the 2nd operand are transferred to the destination operand (dst) specified by the 1st operand. ? after reset release, sp initialization must always be performed with an movg sp, #imm24 instruction after executing the location instruction. [coding example] movg sp, #0ffd20h ; sets 0ffd20h in the sp movg
382 chapter 7 description of instructions add word to g note 24-bit word data addition [instruction format] addwg dst, src note g is a character that indicates that 24-bit data is to be manipulated. [operation] sp sp + word [operands] mnemonic operands (dst, src) addwg sp, #word [flags] s z ac p/v cy [description] ? unsigned 16-bit immediate data is added to the contents of the stack pointer (sp), and the result is stored in the stack pointer (sp). ? this instruction is used to release a memory area reserved as a temporary variable storage location in a high- level language, etc. [coding example] addwg sp, #30h ; adds 30h to the sp and stores the result in the sp addwg
383 chapter 7 description of instructions subtract word from g note 24-bit word data subtraction [instruction format] subwg dst, src note g is a character that indicates that 24-bit data is to be manipulated. [operation] subwg sp sp C 1 [operands] mnemonic operands (dst, src) subwg sp, #word [flags] s z ac p/v cy [description] ? unsigned 16-bit immediate data is subtracted from the contents of the stack pointer (sp), and the result is stored in the sp. ? this instruction is used to reserve a temporary variable area in a high-level language, etc. [coding example] subwg sp, #50h ;subtracts 50h from the sp and stores the result in the sp. this reserves a 50h-byte temporary variable area. subwg
384 chapter 7 description of instructions increment g note stack pointer 24-bit data increment [instruction format] incg sp note g is a character that indicates that 24-bit data is to be manipulated. [operation] sp sp + 1 [operands] none [flags] s z ac p/v cy [description] ? increments the sp (stack pointer) contents by 1. [coding example] incg sp incg sp
385 chapter 7 description of instructions decrement g note stack pointer 24-bit data decrement [instruction format] decg sp note g is a character that indicates that 24-bit data is to be manipulated. [operation] sp sp C 1 [operands] none [flags] s z ac p/v cy [description] ? decrements the sp (stack pointer) contents by 1. [coding example] decg sp decg sp
386 chapter 7 description of instructions 7.16 call/return instructions call/return instructions are as follows: call ... 387 callf ... 388 callt ... 389 brk ... 390 brkcs ... 391 ret ... 393 reti ... 394 retb ... 395 retcs ... 396 retcsb ... 398
387 chapter 7 description of instructions call subroutine call [instruction format] call target [operation] note (sp C 3) (pc + n), sp sp C 3 pc target n: number of instruction bytes note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] mnemonic operands (target) call !addr16 !!addr20 rp rg [rp] [rg] $!addr20 [flags] s z ac p/v cy [description] ? this is a subroutine call using a 16-bit or 20-bit absolute address, 16-bit relative address, register direct address, or register indirect address. ? the start address of the next instruction (pc + n) is saved to the stack, and the program branches to the address specified by the target operand (target). ? if !addr16, rp or [rp] is specified as the operand, the branch destination address is limited to the base area (0 to ffffh) (in the case of [rp], the branch destination table is also limited to the base area). this should only be used when it is absolutely essential to reduce the execution time or object size, and when 78k/0, 78k/i, 78k/ ii, or 78k/iii series software is used and program amendment is difficult. amendments may be necessary in order to make further use of a program that uses these instructions. ? with the nec assembler (ra78k4), if call addr is written, the object code that can be assumed to be most appropriate can be selected and generated automatically from call !addr16, call !!addr20, and call $!addr20. [coding example] call !!13059h ; subroutine call to 013059h call
388 chapter 7 description of instructions call flag subroutine call (11-bit direct specification) [instruction format] callf target [operation] note (sp C 3) (pc + 2), sp sp C 3 pc target note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] mnemonic operands (target) callf !addr11 [flags] s z ac p/v cy [description] ? this is a subroutine call that can branch to addresses 00800h to 00fffh. ? the start address of the next instruction (pc + 2) is saved to the stack, and the program branches to an address in the range 00800h to 00fffh. ? only the low-order 11 bits of the address are specified (the high-order 5 bits are fixed at 00001b). ? locating the subroutine in the area from 00800h to 00fffh and using this instruction enables the program size to be reduced. [coding example] callf !0c2ah ; subroutine call to 00c2ah callf
389 chapter 7 description of instructions call table subroutine call (call table reference) [instruction format] callt [addr5] [operation] note (sp C 3) (pc + 1), sp sp C 3, pc hw 0 pc h (addr5 + 1) pc l (addr5) note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] mnemonic operands ([addr5]) callt [addr5] [flags] s z ac p/v cy [description] ? this is a call table reference subroutine call. ? the start address of the next instruction (pc + 1) is saved to the stack, and the program branches to the address indicated by call table (high-order bits of the address fixed at 0000000001b, next 5 bit specified by addr5, lsb fixed at 0) word data. ? subroutine start addresses that can be branched to by this instruction are limited to the base area (0 to ffffh). [coding example] callt [60h] ; uses the word data in addresses 00060h and 00061h as the address, and makes a subroutine call to that address callt
390 chapter 7 description of instructions break software vectored interrupt [instruction format] brk [operation] (sp C 2) psw, (sp C 4) pc + 1, ie 0 sp sp C 4, pc hw 0, pc lw (003eh) [operands] none [flags] s z ac p/v cy [description] ? this is a software interrupt instruction. ? the psw and the address of the next instruction (pc + 1) are saved to the stack, then the ie flag is cleared (0), and a branch is made to the address specified by the vector address (0003eh) word data (the branch destination address is limited to the base area (0 to ffffh)). ? the retb instruction is used to return from a software vectored interrupt generated by this instruction. [coding example] brk brk
391 chapter 7 description of instructions break context switch software context switch [instruction format] brkcs rbn [operation] pc lw rp2, rp3 psw, pc 15C19 pc 15C19 0 rbs2 C 0 n, rss 0, ie 0 (n = 0 to 7) [operands] mnemonic operands brkcs rbn [flags] s z ac p/v cy [description] ? this is a software interrupt instruction. ? register bank n written in the operand is selected, the contents of rp2 in that register bank and the contents of the low-order 16 bits of the program counter (pc) are exchanged, the contents of the program status word (psw) and the high-order 4 bits of the pc are saved to the stack, the high-order 4 bits of the pc are set to 0, and a branch is made to that address. the rss flag and ie flag are then cleared to 0. ? only addresses in the base area (0 to ffffh) can be branched to by this instruction. ? the retcsb instruction is used to return from a software interrupt generated by this instruction. ? the contents of rp2 and rp3 must not be changed in the software interrupt program initiated by this instruction. if rp2 and rp3 are used, they must be saved to the stack, etc., and returned to their original value before the retcsb instruction is executed. brkcs
392 chapter 7 description of instructions [coding example] brkcs rb3 ; selects register bank 3, and executes instructions from the address indicated by rp2 in register bank 3 00008 7 transfer pc 19C16 pc 15C0 6 exchange 5 save temporary register 2 save (bits 8 to 11 of temporary register) 1 save psw register bank (n = 0 to 7) a b x c rp2 rp3 vp up d h e l v u t w 3 register bank switchover (rbs0-rbs2 ? n) rss ? 0 ie ? 0 4 register bank (0 to 7)
393 chapter 7 description of instructions return return from subroutine [instruction format] ret [operation] note pc (sp), sp sp + 3 note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] none [flags] s z ac p/v cy [description] ? this is the instruction for returning from a subroutine call made by a call, callf, or callt instruction. ? the data saved to the stack is restored to the pc, and a return is made from the subroutine. ret
394 chapter 7 description of instructions return from interrupt return from hardware vectored interrupt [instruction format] reti [operation] note pc (sp), psw (sp + 2), pc sp + 4 the bit set (1) in ispr with the highest priority is cleared (0). note for details, refer to chapter 3, figure 3-4 data saved to stack area, and figure 3-5 data restored from stack area. [operands] none [flags] s z ac p/v cy rr r r r [description] ? this is the instruction for returning from a vectored interrupt. ? the data saved in the stack is restored in pc and psw, and of the flags set (1) in the ispr register, the flag with the highest priority is cleared (0), and operation then returns from the interrupt processing routine. ? this instruction cannot be used to return from a software interrupt generated by a brk instruction, brkcs instruction or operand error, or from an interrupt that uses context switching. reti
395 chapter 7 description of instructions return from break return from software vectored interrupt [instruction format] retb [operation] note pc (sp), psw (sp + 2), pc sp + 4 note for details, refer to chapter 3, figure 3-4 data saved to stack area , and figure 3-5 data restored from stack area. [operands] none [flags] s z ac p/v cy rr r r r [description] ? this is the instruction for returning from a software interrupt generated by an brk instructions operand error. ? the pc and psw saved to the stack are restored, and a return is made from the interrupt service routine. ? this instruction cannot be used to return from a hardware interrupt caused by a brkcs instruction or hardware interrupt retb
396 chapter 7 description of instructions return from context switch return from hardware context switch [instruction format] retcs targer [operation] pc lw rp2, pc 15C19 rp2 8C11 rp2 addr16, psw rp3 the bit set (1) in ispr with the highest priority is cleared (0). [operands] mnemonic operands retcs !addr16 [flags] s z ac p/v cy rr r r r [description] ? the contents of register banks rp2 and rp3 that are specified when this instruction is executed are transferred to the program counter (pc) and program status word (psw), and of the flags set (1) in the ispr register, the flag with the highest priority is cleared (0), and operation then returns from the interrupt processing routine. the data specified by the operand is then transferred to rp2. ? the retcs instruction is valid for context switching associated with generation of an interrupt request, and is used to return from branch processing due to context switching. addr16 written in the operand is the branch address used if the same register bank is specified again by the context switching function (only an address in the base area can be specified as the branch destination address). ? this instruction cannot be used to return from a software interrupt generated by a brk instruction, brkcs instruction or operand error, or from a vectored interrupt. ? before this instruction is executed, the contents of rp2 and rp3 must be the same as immediately after interrupt acknowledgment. retcs
397 chapter 7 description of instructions [coding example] retcs !03456h ; returns from a context switching interrupt, and sets the address for acknowledgment of the next interrupt to 03456h a b x c rp2 rp3 vp up d h e l v u t w register bank (n = 0 to 7) 3 transfer retcs instruction operand pc 19?6 pc 15? psw 4 restore (to original register bank) 2 restore 1 restore
398 chapter 7 description of instructions return from context switch break return from software context switch [instruction format] retcsb targer [operation] pc lw rp2, pc 15C19 rp3 8C11 rp2 addr16, psw rp3 [operands] mnemonic operands retcsb !addr16 [flags] s z ac p/v cy rr r r r [description] ? the contents of rp2 and rp3 in the register bank specified when this instruction is executed are transferred to the program counter (pc) and program status word (psw), and a return is made from the interrupt service routine. the data specified by the operand is then transferred to rp2. ? the retcsb instruction is valid for context switching by means of the brkcs instruction, and is used to return from branch processing due to context switching. addr16 written in the operand is the branch address used if the same register bank is specified again by the context switching function (only an address in the base area can be specified as the branch destination address). ? this instruction cannot be used to return from a software interrupt generated by a brk instruction or operand error, or from a hardware interrupt. ? before this instruction is executed, the contents of rp2 and rp3 must be the same as immediately after interrupt acknowledgment. retcsb
399 chapter 7 description of instructions [coding example] retcsb !0abcdh ; returns from an interrupt generated by a brkcs instruction a b x c rp2 rp3 vp up d h e l v u t w register bank (n = 0 to 7) 3 transfer retcsb instruction operand pc 19?6 pc 15? psw 4 restore (to original register bank) 2 restore 1 restore
400 chapter 7 description of instructions 7.17 unconditional branch instruction there is one unconditional branch instruction, as follows. br ... 401
401 chapter 7 description of instructions branch unconditional branch [instruction format] br target [operation] pc target [operands] mnemonic operands (target) br !addr16 !!addr20 rp rg [rp] [rg] $addr20 $!addr20 [flags] s z ac p/v cy [description] ? instruction that performs an unconditional branch. ? the target address operand (target) data is transferred to the pc, and a branch is made. ? if !addr16, rp or [rp] is specified as the operand, the branch destination address is limited to the base area (0 to ffffh) (in the case of [rp], the branch destination table is also limited to the base area). this should only be used when it is absolutely essential to reduce the execution time or object size, and when a 78k/0, 78k/i, 78k/ii, or 78k/iii series software is used and program amendment is difficult. amendments may be necessary in order to make further use of a program that uses these instructions. ? with the nec assembler ra78k4, if br addr is written, the object code that can be assumed to be most appropriate can be selected and generated automatically from br $addr20, br $!addr20, br !addr16, and br!!addr20. [coding example] br tde ; branches using the contents of the tde register as the address br
402 chapter 7 description of instructions 7.18 conditional branch instructions conditional branch instructions are as follows: bnz ... 403 bne ... 403 bz ... 404 be ... 404 bnc ... 405 bnl ... 405 bc ... 406 bl ... 406 bnv ... 407 bpo ... 407 bv ... 408 bpe ... 408 bp ... 409 bn ... 410 blt ... 411 bge ... 412 ble ... 413 bgt ... 414 bnh ... 415 bh ... 416 bf ... 417 bt ... 418 btclr ... 419 bfset ... 420 dbnz ... 421
403 chapter 7 description of instructions branch if not zero/not equal conditional branch upon zero flag (z = 0) [instruction format] bnz $addr20 bne $addr20 [operation] pc pc + 2 + jdisp8 if z = 0 [operands] mnemonic operands ($addr20) bnz $addr20 bne [flags] s z ac p/v cy [description] ? if z = 0, the program branches to the address specified by the operand. if z = 1, no processing is performed and the next instruction is executed. ? the operation of the bnz instruction and the bne instruction is the same. they are used as follows: C bnz instruction: to check whether the result of an addition, subtraction or increment/decrement instruction, or an 8-bit logical operation or shift/rotate instruction is 0. C bne instruction: checks for a match after a compare instruction. ? if two C80h values are added together in the case of 8 bits when twos complement type data addition is performed, or two C8000h values in the case of 16 bits, z is set to 1. when determining whether or not the result of a twos complement type data addition is 0, check for overflow beforehand using the overflow flag (v). [coding example] cmp a, #55h bne $0a39h ; branches to 00a39h if the a register is not 0055h the start address of the bne instruction must be in the range 009b8h to 00ab7h bnz bne
404 chapter 7 description of instructions branch if zero/equal than conditional branch upon zero flag (z = 1) [instruction format] bz $addr20 be $addr20 [operation] pc pc + 2 + jdisp8 if z = 1 [operands] mnemonic operands ($addr20) bz $addr20 be [flags] s z ac p/v cy [description] ? if z = 1, the program branches to the address specified by the operand. if z = 0, no processing is performed and the next instruction is executed. ? the operation of the bz instruction and the be instruction is the same. they are used as follows: C bz instruction: to check whether the result of an addition, subtraction or increment/decrement instruction, or an 8-bit logical operation or shift/rotate instruction is 0. C be instruction: checks for a match after a compare instruction. ? if two C80h values are added together in the case of 8 bits when twos complement type data addition is performed, or two C8000h values in the case of 16 bits, z is set to 1. when determining whether or not the result of a twos complement type data addition is 0, check for overflow beforehand using the overflow flag (v). [coding example] dec b bz $3c5h ; branches to 003c5h if the b register is 0 the start address of the bz instruction must be in the range 00344h to 00443h bz be
405 chapter 7 description of instructions branch if not carry/less than conditional branch upon carry flag (cy = 0) [instruction format] bnc $addr20 bnl $addr20 [operation] pc pc + 2 + jdisp8 if cy = 0 [operands] mnemonic operands ($addr20) bnc $addr20 bnl [flags] s z ac p/v cy [description] ? if cy = 0, the program branches to the address specified by the operand. if cy = 1, no processing is performed and the next instruction is executed. ? the operation of the bnc instruction and the bnl instruction is the same. differences in their use are as follows: C bnc instruction: checks whether a carry has been generated after an addition or shift/rotate instruction. determines the result of bit manipulation. C bnl instruction: checks whether a borrow has been generated after a subtraction instruction. after a compare instruction on unsigned data, checks whether or not the 1st operand of the compare instruction is smaller. [coding example] cmp a, b ; compares the size of the a register contents and b register contents bnl $1500h ; branches to 01500h if the a register contents are smaller than the b register contents the start address of the bnl instruction must be in the range 0147fh to 0157eh bnc bnl
406 chapter 7 description of instructions branch if carry/less than conditional branch upon carry flag (cy = 1) [instruction format] bc $addr20 bl $addr20 [operation] pc pc + 2 + jdisp8 if cy = 1 [operands] mnemonic operands ($addr20) bc $addr20 bl [flags] s z ac p/v cy [description] ? if cy = 1, the program branches to the address specified by the operand. if cy = 0, no processing is performed and the next instruction is executed. ? the operation of the bc instruction and the bl instruction is the same. they are used as follows: C bc instruction : checks whether a carry has been generated after an addition or shift/rotate instruction. determines the result of bit manipulation. C bl instruction : checks whether a borrow has been generated after a subtraction instruction. after a compare instruction on unsigned data, checks whether or not the 1st operand of the compare instruction is smaller. [coding example] bc $300h ; branches to 00300h if cy = 1 the start address of the bc instruction must be in the range 0027fh to 0037eh bc bl
407 chapter 7 description of instructions branch if no overflow/branch if parity odd conditional branch upon parity/overflow flag (p/v = 0) [instruction format] bnv $addr20 bpo $addr20 [operation] pc pc + 2 + jdisp8 if p/v = 0 [operands] mnemonic operands ($addr20) bnv $addr20 bpo [flags] s z ac p/v cy [description] ? if p/v = 0, the program branches to the address specified by the operand. if p/v = 1, no processing is performed and the next instruction is executed. ? the operation of the bnv instruction and the bpo instruction is the same. they are used as follows: C bnv instruction : checks that the result has neither overflowed nor underflowed after an operation of twos complement format data, etc. C bpo instruction : checks that the parity of the logical operation instruction or shift rotate instruction execution result is odd. [coding example] add b, c ; adds together the contents of the b register and c register (twos complement type data) bnv $560h ; branches to 560h if there is no overflow in the result of the addition the start address of the bnv instruction must be in the range 004dfh to 05deh bnv bpo
408 chapter 7 description of instructions branch if overflow/branch if parity even conditional branch upon parity/overflow flag (p/v = 1) [instruction format] bv $addr20 bpe $addr20 [operation] pc pc + 2 + jdisp8 if p/v = 1 [operands] mnemonic operands ($addr20) bv $addr20 bpe [flags] s z ac p/v cy [description] ? if p/v = 1, the program branches to the address specified by the operand. if p/v = 0, no processing is performed and the next instruction is executed. ? the operation of the bv instruction and the bpe instruction is the same. they are used as follows: C bv instruction : checks that the result has overflowed or underflowed after an operation of twos complement format data, etc. C bpe instruction : checks that the parity of the logical operation instruction or shift rotate instruction execution result is even. [coding example] or d, #055h ; finds the bit-wise logical sum of the d register contents and 055h bpe $841eh ; branches to 841eh if the parity is even as a result of finding the logical sum the start address of this instruction must be in the range 839dh to 849ch bv bpe
409 chapter 7 description of instructions branch if positive conditional branch upon sign flag (s = 0) [instruction format] bp $addr20 [operation] pc pc + 2 + jdisp8 if s = 0 [operands] mnemonic operands ($addr20) bp $addr20 [flags] s z ac p/v cy [description] ? if s = 0, the program branches to the address specified by the operand. if s = 1, no processing is performed and the next instruction is executed. ? this instruction is used to check whether the result is positive (including 0) after a twos complement type data operation. however, a correct judgment cannot be made if the operation result overflows or underflows; therefore, a bv instruction or bnv instruction should be used beforehand to check that there is no overflow or underflow, or the bge instruction should be used. [coding example] bv $over ; branches to address over, if the operation result overflows or underflows bp $target ; branches to address target if the operation result is positive (including 0) address target must be within C126 to +129 of the start address of the bp instruction bp
410 chapter 7 description of instructions branch if negative conditional branch upon sign flag (s = 1) [instruction format] bn $addr20 [operation] pc pc + 2 + jdisp8 if s = 1 [operands] mnemonic operands ($addr20) bn $addr20 [flags] s z ac p/v cy [description] ? if s = 1, the program branches to the address specified by the operand. if s = 0, no processing is performed and the next instruction is executed. ? this instruction is used to check whether the result is negative after a twos complement type data operation. however, a correct judgment cannot be made if the operation result overflows or underflows; therefore, a bv instruction or bnv instruction should be used beforehand to check that there is no overflow or underflow, or the blt instruction should be used. [coding example] bn #target ; branches to address target if the operation result is negative bn
411 chapter 7 description of instructions branch if less than conditional branch upon size of number (less than ... ) [instruction format] blt $addr20 [operation] pc pc + 3 + jdisp8 if p/v s = 1 [operands] mnemonic operands ($addr20) blt $addr20 [flags] s z ac p/v cy [description] ? if p/v s = 1, the program branches to the address specified by the operand. if p/v s = 0, no processing is performed and the next instruction is executed. ? this instruction is used to determine the relative size of twos complement type data, or to check whether the result of an operation is negative. in relative size determination, the instruction checks whether the 1st operand of the cmp instruction executed immediately before is smaller than the 2nd operand. this instruction is also used to check whether the operation result is negative, including the case where underflow has occurred. [coding example] cmpw ax, #3456h blt $8123h ; branches to address 8123h if the contents of the ax register are less than 3456h the start address of the blt instruction must be in the range 80a1h to 81a0h blt
412 chapter 7 description of instructions branch if greater than/equal conditional branch upon size of number (greater than or equal to ... ) [instruction format] bge $addr20 [operation] pc pc + 3 + jdisp8 if p/v s = 0 [operands] mnemonic operands ($addr20) bge $addr20 [flags] s z ac p/v cy [description] ? if p/v s = 0, the program branches to the address specified by the operand. if p/v s = 1, no processing is performed and the next instruction is executed. ? this instruction is used to determine the relative size of twos complement type data, or to check whether the result of an operation is 0 or positive. in relative size determination, the instruction checks whether the 1st operand of the cmp instruction executed immediately before is greater than the 2nd operand. this instruction is also used to check whether the operation result is 0 or greater, including the case where overflow has occurred. [coding example] addw ax, bc bge $23456h ; branches to address 23456h if the result of the immediately preceding addition instruction is 0 or greater the start address of the bge instruction must be in the range 233d4h to 234d3h bge
413 chapter 7 description of instructions branch if less than/equal conditional branch upon size of number (less than or equal to ... ) [instruction format] ble $addr20 [operation] pc pc + 3 + jdisp8 if (p/v s) z = 1 [operands] mnemonic operands ($addr20) ble $addr20 [flags] s z ac p/v cy [description] ? if (p/v s) z = 1, the program branches to the address specified by the operand. if (p/v s) z = 0, no processing is performed and the next instruction is executed. ? this instruction is used to determine the relative size of twos complement type data, or to check whether the result of an operation is negative, including 0. in relative size determination, the instruction checks whether the 1st operand of the cmp instruction executed immediately before is smaller than the 2nd operand. this instruction is also used to check whether the operation result is negative, including the case where underflow has occurred. [coding example] sub h, l ble $789abh ; branches to 789abh if the result of the immediately preceding subtraction instruction is 0 or less, including the case where underflow has occurred the start address of the bl instruction must be in the range 78929h to 789abh ble
414 chapter 7 description of instructions branch if greater than conditional branch upon size of number (greater than ... ) [instruction format] bgt $addr20 [operation] pc pc + 3 + jdisp8 if (p/v s) z = 0 [operands] mnemonic operands ($addr20) bgt $addr20 [flags] s z ac p/v cy [description] ? if (p/v s) z = 0, the program branches to the address specified by the operand. if (p/v s) z = 1, no processing is performed and the next instruction is executed. ? this instruction is used to determine the relative size of twos complement type data, or to check whether the result of an operation is greater than 0. in relative size determination, the instruction checks whether the 1st operand of the cmp instruction executed immediately before is greater than the 2nd operand. this instruction is also used to check whether the operation result is greater than 0, including the case where overflow has occurred. [coding example] cmp a, e bgt $0cffedh ;branches to address 0cffedh if the contents of the a register are greater than the contents of the b register the start address of the bgt instruction must be in the range 0cff6bh to 0d006dh bgt
415 chapter 7 description of instructions branch if not higher than conditional branch upon size of number (not higher than ... ) [instruction format] bnh $addr20 [operation] pc pc + 3 + jdisp8 if z cy = 1 [operands] mnemonic operands ($addr20) bnh $addr20 [flags] s z ac p/v cy [description] ? if z cy = 1, the program branches to the address specified by the operand. if z cy = 0, no processing is performed and the next instruction is executed. ? this instruction is used to determine the relative size of unsigned data. the instruction checks whether the 1st operand of the cmp instruction executed immediately before is not greater than the 2nd operand (i.e. the 1st operand is the same as or smaller than the 2nd operand). [coding example] cmpw rp2, #8921h bnh $target ; branches to address target if the contents of the rp2 register are not greater than 8921h (equal to or less than 8912h) the start address of the bnh instruction must be an address from which a branch can be made to address target bnh
416 chapter 7 description of instructions branch if higher than conditional branch upon size of number (higher than ... ) [instruction format] bh $addr20 [operation] pc pc + 3 + jdisp8 if z cy = 0 [operands] mnemonic operands ($addr20) bh $addr20 [flags] s z ac p/v cy [description] ? if z cy = 0, the program branches to the address specified by the operand. if z cy = 1, no processing is performed and the next instruction is executed. ? this instruction is used to determine the relative size of unsigned data. the instruction checks whether the 1st operand of the cmp instruction executed immediately before is greater than the 2nd operand. [coding example] cmp b, c bh $356h ; branches to 356h if the contents of the b register are greater than the contents of the c register the start address of the bh instruction must be in the range 2d4h to 3d3h bh
417 chapter 7 description of instructions branch if false conditional branch depending on bit test (byte data bit = 0) [instruction format] bf bit, $addr20 [operation] pc pc + b + jdisp8 if bit = 0 [operands] mnemonic operands (bit, $addr20) b (number of bytes) bf saddr.bit, $addr20 4/5 sfr.bit, $addr20 4 x.bit, $addr20 3 a.bit, $addr20 3 pswl.bit, $addr20 3 pswh.bit, $addr20 3 mem2.bit, $addr20 3 !addr16.bit, $addr20 6 !!addr24.bit, $addr20 7 [flags] s z ac p/v cy [description] ? if the contents of the 1st operand (bit) are cleared (0), the program branches to the address specified by the 2nd operand ($addr20). if the contents of the 1st operand (bit) are not cleared (0), no processing is performed and the next instruction is executed. [coding example] bf p2.2, $1549h ; branches to address 01549h if bit 2 of port 2 is 0 the start address of the bf instruction must be in the range 014c6h to 015c5h bf
418 chapter 7 description of instructions branch if true conditional branch depending on bit test (byte data bit = 1) [instruction format] bt bit, $addr20 [operation] pc pc + b + jdisp8 if bit = 1 [operands] mnemonic operands (bit, $addr20) b (number of bytes) bf saddr.bit, $addr20 3/4 sfr.bit, $addr20 4 x.bit, $addr20 3 a.bit, $addr20 3 pswl.bit, $addr20 3 pswh.bit, $addr20 3 mem2.bit, $addr20 3 !addr16.bit, $addr20 6 !!addr24.bit, $addr20 7 [flags] s z ac p/v cy [description] ? if the contents of the 1st operand (bit) are set (1), the program branches to the address specified by the 2nd operand ($addr16). if the contents of the 1st operand (bit) are not set (1), no processing is performed and the next instruction is executed. [coding example] bt 0fe47h.3, $55ch ; branches to 0055ch if bit 3 of address 0fe47h the start address of the bt instruction must be in the range 004d9h to 005d8h bt
419 chapter 7 description of instructions branch if true and clear conditional branch and clear depending on bit test (byte data bit = 1) [instruction format] btclr bit, $addr20 [operation] pc pc + b + jdisp8 if bit = 1, then bit 0 [operands] mnemonic operands (bit, $addr20) b (number of bytes) btclr saddr.bit, $addr20 4/5 sfr.bit, $addr20 4 x.bit, $addr20 3 a.bit, $addr20 3 pswl.bit, $addr20 3 pswh.bit, $addr20 3 mem2.bit, $addr20 3 !addr16.bit, $addr20 6 !!addr24.bit, $addr20 7 [flags] bit is pswl.bit in other cases s z ac p/v cy s z ac p/v cy [description] ? if the contents of the 1st operand (bit) are set (1), the contents of the 1st operand (bit) are cleared (0), and the program branches to the address specified by the 2nd operand. if the contents of the 1st operand (bit) are not set (1), no processing is performed and the next instruction is executed. ? if the 1st operand (bit) is psw.bit, the contents of the relevant flag are cleared (0). [coding example] btclr psw.0, $356h ;if bit 0 of the psw (cy flag) is 1, clears (0) the cy flag and branches to address 00356h the start address of the btclr instruction must be in the range 002d4h to 003d3h btclr
420 chapter 7 description of instructions branch if false and set conditional branch and set depending on bit test (byte data bit = 0) [instruction format] bfset bit, $addr20 [operation] pc pc + b + jdisp8 if bit = 0, then bit 1 [operands] mnemonic operands (bit, $addr20) b (number of bytes) bfset saddr.bit, $addr20 4/5 sfr.bit, $addr20 4 x.bit, $addr20 3 a.bit, $addr20 3 pswl.bit, $addr20 3 pswh.bit, $addr20 3 mem2.bit, $addr20 3 !addr16.bit, $addr20 6 !!addr24.bit, $addr20 7 [flags] bit is pswl.bit in other cases s z ac p/v cy s z ac p/v cy [description] ? if the contents of the 1st operand (bit) are cleared (0), the contents of the 1st operand (bit) are set (1), and the program branches to the address specified by the 2nd operand. if the contents of the 1st operand (bit) are set (1), no processing is performed and the next instruction is executed. ? if the 1st operand (bit) is psw.bit, the contents of the relevant flag are set (1). [coding example] bfset a.6, $3ffe1h ;if bit 6 of the a register is 0, sets (1) bit 6 of the a register and branches to address 3ffe1h the start address of the bfset instruction must be in the range 3ff5fh to 4005eh bfset
421 chapter 7 description of instructions decrement and branch if not zero conditional loop (dst 0) [instruction format] dbnz dst, $addr20 [operation] dst dst C 1, then pc pc + b + jdisp8 if dst 0 [operands] mnemonic operands (bit, $addr20) b (number of bytes) dbnz b, $addr20 2 c, $addr20 2 saddr, $addr20 3/4 [flags] s z ac p/v cy [description] ? the contents of the destination operand (dst) specified by the 1st operand are decremented by 1, and the program branches to the destination operand (dst). ? if the result of decrementing the destination operand (dst) by 1 is not 0, the program branches to the address indicated by the 2nd operand ($addr20). if the result of decrementing the destination operand (dst) by 1 is 0, no processing is performed and the next instruction is executed. ? flags are not changed. [coding example] dbnz b, $1215h ; decrements the contents of the b register, and if 0, branches to 001215h the start address of the dbnz instruction must be in the range 001194h to 001293h dbnz
422 chapter 7 description of instructions 7.19 cpu control instructions cpu control instructions are as follows: mov stbc, #byte ... 423 mov wdm, #byte ... 424 location ... 425 sel rbn ... 426 sel rbn, alt ... 427 swrs ... 428 nop ... 429 ei ... 430 di ... 431
423 chapter 7 description of instructions move standby mode setting [instruction format] mov stbc #byte [operation] stbc byte [operands] mnemonic operands mov stbc, #byte [flags] s z ac p/v cy [description] ? this a special instruction for writing to the standby control register (stbc). the immediate data specified by the 2nd operand is written to stbc. the stbc register can only be written to by means of this instruction. ? this instruction has a special format, and in addition to the immediate data used to perform the write, the logical not of that value must also be provided in the operation code (see figure below). (this is generated automatically by the nec assembler (ra78k4).) C operation code format ? the cpu checks the immediate data to be used for the write and the logical not data, and only performs the write if they are correct. if they are not correct, the write is not performed and an operand error interrupt is generated. [coding example] mov stbc, #2 ; writes 2 to stbc (sets the stop mode) mov stbc, #byte 0 0 0 0 1 0 0 1 1 1 0 0 0 0 0 0 byte byte
424 chapter 7 description of instructions move watchdog timer setting [instruction format] mov wdm #byte [operation] wdm byte [operands] mnemonic operands mov wdm, #byte [flags] s z ac p/v cy [description] ? this a special instruction for writing to the watchdog timer mode register (wdm). the immediate data specified by the 2nd operand is written to wdm. the wdm register can only be written to by means of this instruction. ? this instruction can only be used with a product that incorporates a watchdog timer. please refer to the users manual hardware volume for the relevant product to see whether a watchdog timer is incorporated. ? this instruction has a special format, and in addition to the immediate data used to perform the write, the logical not of that value must also be provided in the operation code (see figure below). (this is generated automatically by the nec assembler (ra78k4).) C operation code format ? the cpu checks the immediate data to be used for the write and the logical not data, and only performs the write if they are correct. if they are not correct, the write is not performed and an operand error interrupt is generated. [coding example] mov wdm, #0c0h ; writes 0c0h to wdm mov wdm, #byte 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 byte byte
425 chapter 7 description of instructions location location [instruction format] location locaddr [operation] sfr & internal data area location address upper word specification [operands] mnemonic operands location locaddr [flags] s z ac p/v cy [description] ? this instruction is used to specify the address of the internal data area (internal ram and special function registers (sfrs)). if 0 is specified, the maximum address of the internal data area is 0ffffh, and if 0fh is specified, the maximum address of the internal data area is 0fffffh. ? an interrupt or macro service request is not acknowledged between this instruction and the next instruction. ? this instruction must always be executed immediately after reset release. that is, this instruction must be located in the address specified by the reset vector. this instruction cannot be used more than once. if executed more than once, an address in the internal data area cannot be changed in the second or subsequent executions. ? the operand for this instruction is coded as shown below. locaddr operand code 0h 01feh 0fh 00ffh execution of this instruction is ignored if a different value is specified. also, an operand error interrupt is generated if the exclusive logical sum of the upper byte and lower byte of the operand is not 0ffh. [coding example] location 0fh ; sets the maximum address of the internal data area to 0fffffh location
426 chapter 7 description of instructions select register bank register bank selection [instruction format] sel rbn [operation] rss 0, rbs2 C 0 n ; (n = 0 C 3) [operands] mnemonic operands (rbn) sel rbn [flags] s z ac p/v cy [description] ? selects the register bank specified by the operand (rbn) as the register bank to be used from the next instruction onward. ? the range for rbn is rb0 to rb7. [coding example] sel rb2 ; selects register bank 2 as the register bank to be used from the next instruction onward. sel rbn
427 chapter 7 description of instructions select register bank register bank selection [instruction format] sel rbn, alt [operation] rss1 1, rbs2 C 0 n ; (n = 0 C 3) [operands] mnemonic operands sel rbn, alt [flags] s z ac p/v cy [description] ? selects the register bank specified by the 1st operand (rbn) as the register bank to be used from the next instruction onward, and also sets (1) the register selection flag (rss). ? the range for rbn is rb0 to rb7. ? this instruction is provided to maintain compatibility with the 78k/iii series, and can only be used when a 78k/ iii series program is used. it should not be used when using a program for a 78k series other than the 78k/ iii series or when using a newly written program. sel rbn, alt
428 chapter 7 description of instructions switch register set register bit switching [instruction format] swrs [operation] rss rss [operands] none [flags] s z ac p/v cy [description] ? inverts the contents of the register set selection flag (rss). ? this instruction is provided to maintain compatibility with the 78k/iii series, and can only be used when a 78k/ iii series program is used. it should not be used when using a program for a 78k series other than the 78k/ iii series or when using a newly written program. swrs
429 chapter 7 description of instructions no operation no operation [instruction format] nop [operation] no operation [operands] none [flags] s z ac p/v cy [description] ? this instruction simply consumes time without performing any processing. nop
430 chapter 7 description of instructions enable interrupt interrupt enabling [instruction format] ei [operation] ie 1 (enable interrupt) [operands] none [flags] s z ac p/v cy [description] ? sets the state in which maskable interrupts can be acknowledged (sets (1) the interrupt enable flag (ie)). ? no interrupts or macro service requests are acknowledged for a certain period after execution of this instruction. please refer to the users manual hardware volume for the relevant product for details. ? it is possible to arrange for acknowledgment of vectored interrupts from other sources not to be performed even though this instruction is executed. please refer to the users manual hardware volume for the individual products for details. ei
431 chapter 7 description of instructions disable interrupt interrupt disabling [instruction format] di [operation] ie 0 (disable interrupt) [operands] none [flags] s z ac p/v cy [description] ? disables acknowledgment by vectored interrupts among maskable interrupts (clears (0) the interrupt enable flag (ie)). ? no interrupts or macro service requests are acknowledged for a certain period after execution of this instruction. please refer to the users manual hardware volume for the relevant product for details. ? please refer to the users manual hardware volume for the individual products for details of interrupt servicing. di
432 chapter 7 description of instructions 7.20 special instructions special instructions are as follows. chkl ... 433 chkla ... 434
433 chapter 7 description of instructions check level pin output level check [instruction format] chkl sfr [operation] (pin level) (output latch) [operands] mnemonic operands chkl sfr [flags] s z ac p/v cy p [description] ? the exclusive logical sum of the output pin level and output buffer prestage signal level is found. ? the s flag is set (1) if bit 7 is set (1) as a result of the exclusive logical sum operation, and s flag is cleared (0) if bit 7 is cleared (0). ? the z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and z flag is cleared (0) if there are non-zero bits. ? the p/v flag is set (1) if the number of bits in the data set (1) as a result of the exclusive logical sum operation is even, and cleared (0) if the number is odd. ? this instruction is used to detect an abnormal state which has arisen for some reason or other in which the output pin level and the output buffer prestage signal level are different. in normal operation, the z flag is always set (1). ? when this instruction is executed, with a product that has a port read control register (prdc), the prdc0 bit of the prdc register must be cleared (0). an abnormal state cannot be detected if the prdc0 bit is set (1). ? when this instruction is executed on a port that includes a pin used as a control output, the input/output mode for the port with a pin used as a control output must be set to input mode. if the input/output mode for a port with a pin used as a control output is set to output mode, operation may be judged to be abnormal even though it is normal. ? a pin for which the input/output mode as a port is specified as the input mode will always be judged to be normal by this instruction. [coding example] chkl p0 bnz $error ; checks whether the port 0 pin level and output buffer prestage signal level match, and if they do not, branches to address error caution the chkl instruction is not available in the m pd784216, 784216y, 784218, 784218y, 784225, 784225y, 784937 subseries. do not execute this instruction. if this instruction is executed, the following condition will result. ? after the pin levels of output pins are read two times, they are exclusive-ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1). chkl
434 chapter 7 description of instructions check level and transfer to register pin output level check and transfer to register [instruction format] chkla sfr [operation] a (pin level) (output latch) [operands] mnemonic operands chkla sfr [flags] s z ac p/v cy p [description] ? the exclusive logical sum of the output pin level and output buffer prestage signal level is found, and the result is stored in the a register. ? the s flag is set (1) if bit 7 is set (1) as a result of the exclusive logical sum operation, and s flag is cleared (0) if bit 7 is cleared (0). ? the z flag is set (1) if all bits are 0 as a result of the exclusive logical sum operation, and z flag is cleared (0) if there are non-zero bits. ? the p/v flag is set (1) if the number of bits in the data set (1) as a result of the exclusive logical sum operation is even, and cleared (0) if the number is odd. ? this instruction is used to detect an abnormal state which has arisen for some reason or other in which the output pin level and the output buffer prestage signal level are different. in normal operation, the z flag is always set (1). ? when this instruction is executed, with a product that has a port read control register (prdc), the prdc0 bit of the prdc register must be cleared (0). an abnormal state cannot be detected if the prdc0 bit is set (1). ? when this instruction is executed on a port that includes a pin used as a control output, the input/output mode for the port with a pin used as a control output must be set to input mode. if the input/output mode for a port with a pin used as a control output is set to output mode, operation may be judged to be abnormal even though it is normal. ? a pin for which the input/output mode as a port is specified as the input mode will always be judged to be normal by this instruction. [coding example] chkla p3 ; checks whether the port 3 pin level and output buffer prestage signal level match, and stores the result in the a register caution the chkla instruction is not available in the m pd784216, 784216y, 784218, 784218y, 784225, 784225y, 784937 subseries. do not execute this instruction. if this instruction is executed, the following condition will result. ? after the pin levels of output pins are read two times, they are exclusive-ored. as a result, if the pins checked with this instruction are used in the port output mode, the exclusive-or result is always 0 for all bits, and the z flag is set to (1) along with that the result is saved in the a register. chkla
435 chapter 7 description of instructions 7.21 string instructions string instructions are as follows. movtblw ... 436 movm ... 438 xchm ... 440 movbk ... 442 xchbk ... 445 cmpme ... 448 cmpmne ... 451 cmpmc ... 454 cmpmnc ... 457 cmpbke ... 460 cmpbkne ... 463 cmpbkc ... 466 cmpbknc ... 469
436 chapter 7 description of instructions move table word table word transfer [instruction format] movtblw !addr8, byte [operation] (addr8 + 2) (addr8), byte byte C 1, addr8 addr8 C 2, end if byte = 0 [operands] mnemonic operands movtblw !addr16, byte [flags] s z ac p/v cy [description] ? the contents of the memory addressed by the 16 bits immediate data specified by the 1st operand are transferred to the address incremented by 2. addr8 is then decremented by 2. the above operations are repeated the number of times indicated by the 8 bits immediate data written as the 2nd operand. ? this instruction is used to shift the data table used by the macw and macsw instructions. ? the address of the most significant data of the data on which the transfer is to be performed is written directly in the 1st operand !addr8 as a label or number. ? the address written as the 1st operand must be in the range 00fe00h to 00feffh when a location 0 instruction is executed, or in the range 0ffe00h to 0ffeffh when a location 0fh instruction is executed. remark the m pd784915 subseries is fixed to the location 0 instruction. movtblw
437 chapter 7 description of instructions [coding example] movtblw !0ffe60h, 5 ; transfers the data in 0ffe58h through 0ffe60h to 0ffe5ah through 0ffe62h 15 0 before execution 0ba98h 0123h 4567h 89abh 0cdefh 0fedch 0fe60h 5 words 0fe58h 15 0 after execution 0123h 4567h 89abh 0cdefh 0fedch 0fedch 0fe62h 0fe60h 0fe58h movtblw end no byte = 0? yes (addr8 + 2) (addr8) addr8 addr8 ?2 byte byte ?1
438 chapter 7 description of instructions move multiple byte block transfer of fixed byte data [instruction format] movm [tde +], a movm [tde C], a [operation] (tde) a, tde tde + 1, c c C 1 end if c = 0 (tde) a, tde tde C 1, c c C 1 end if c = 0 [operands] mnemonic operands movm [tde + ], a [tde C ], a [flags] s z ac p/v cy [description] ? the contents of the a register are transferred to the memory addressed by the tde register, and the contents of the tde register are incremented/decremented. the contents of the c register are then decremented, and the above operations are repeated until the contents of the c register are 0. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? this instruction is mainly used to initialize a certain area of memory with a specific value. the movbk instruction is used to perform initialization with multi-byte data. movm
439 chapter 7 description of instructions [coding example] mov c, #00h ; c 00h mov a, #00h ; a 00h movg tde, #0fe00h ; tde fe00h movm [tde +], a ; clears ram fe00h to feffh c byte tde 0 7 a register movm acknowledgeable interrupt or macro service request? no (tde) a tde tde 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "?
440 chapter 7 description of instructions exchange multiple byte block exchange of fixed byte data [instruction format] xchm [tde + ], a xchm [tde C ], a [operation] (tde) a, tde tde + 1, c c C 1 end if c = 0 (tde) a, tde tde C 1, c c C 1 end if c = 0 [operands] mnemonic operands xchm [tde + ], a [tde C ], a [flags] s z ac p/v cy [description] ? the contents of the a register are exchanged with the contents of the memory addressed by the tde register, and the contents of the tde register are incremented/decremented. the contents of the c register are then decremented, and the above operations are repeated until the contents of the c register are 0. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? this instruction is mainly used to perform a one-byte move of data in memory. xchm [tde + ], a is used for a move in the upper address direction, and xchm [tde C ], a for a move in the low-order address direction. the movbk instruction is used to move two or more bytes. xchm
441 chapter 7 description of instructions [coding example] mov c, #10h ; c 10h mov a, #00h ; a 00h movg tde, #3050h ; tde 3050h xchm [tde +], a ; shifts the contents of memory 3050h through 305fh one address at a time into the addresses behind (the contents of address 3050h become 0) c byte tde 0 7 a register xchm acknowledgeable interrupt or macro service request? no (tde) a tde tde 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "?
442 chapter 7 description of instructions move block byte byte data block transfer [instruction format] movbk [tde +], [whl + ] movbk [tde C ], [whl C ] [operation] (tde) (whl), tde tde + 1, whl whl + 1 c c C 1 end if c = 0 (tde) (whl), tde tde C 1, whl whl C 1 c c C 1 end if c = 0 [operands] mnemonic operands movbk [tde + ], [whl + ] [tde C ], [whl C ] [flags] s z ac p/v cy [description] ? the contents of the memory addressed by the whl register are transferred to the memory addressed by the tde register, and the contents of the tde and whl registers are incremented/decremented. the contents of the c register are then decremented, and the above operations are repeated until the contents of the c register are 0. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde, whl, and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? if the transfer source data area and transfer destination data area overlap, the operation is as follows. C if the minimum address of the transfer source is smaller than the maximum address of the transfer destination, the respective minimum addresses are used as the initial values for both the tde and the whl register, and movbk [tde + ], [whl + ] is used. C if the maximum address of the transfer source is greater than the minimum address of the transfer destination, the respective maximum addresses are used as the initial values for both the tde and the whl register, and movbk [tde C ], [whl C ] is used. movbk
443 chapter 7 description of instructions c byte whl 0 7 tde movbk acknowledgeable interrupt or macro service request? no (tde) (whl) tde tde 1 note whl whl 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "?
444 chapter 7 description of instructions [coding example] mov c, #10h ; c 10h movg tde, #3000h ; tde 3000h movg whl, #5000h ; whl 5000h movbk [tde + ], [whl + ] ; transfers the contents of memory 5000h through 500fh to memory 3000h through 300fh
445 chapter 7 description of instructions exchange block byte byte data block exchange [instruction format] xchbk [tde +], [whl + ] xchbk [tde C ], [whl C ] [operation] (tde) (whl), tde tde + 1, whl whl + 1 c c C 1 end if c = 0 (tde) (whl), tde tde C 1, whl whl C 1 c c C 1 end if c = 0 [operands] mnemonic operands xchbk [tde + ], [whl + ] [tde C ], [whl C ] [flags] s z ac p/v cy [description] ? the contents of the memory addressed by the whl register are exchanged with the contents of the memory addressed by the tde register, and the contents of the whl and tde registers are incremented/decremented. the contents of the c register are then decremented, and the above operations are repeated until the contents of the c register are 0. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde, whl, and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. xchbk
446 chapter 7 description of instructions xchbk acknowledgeable interrupt or macro service request? no (tde) (whl) tde tde 1 note whl whl 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? c byte whl 0 7 tde
447 chapter 7 description of instructions [coding example] mov c, #80h movg tde, #3456h movg whl, #1ff96h xchbk [tde + ], [whl + ] ; exchanges the 80h-byte data from address 3456h with the data from address 1ff96h
448 chapter 7 description of instructions compare multiple equal byte block comparison with fixed byte data (match detection) [instruction format] cmpme [tde + ], a cmpme [tde C ], a [operation] (tde) C a, tde tde + 1, c c C 1 end if c = 0 or z = 0 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or z = 0 [operands] mnemonic operands cmpme [tde + ], a [tde C ], a [flags] s z ac p/v cy v [description] ? the contents of the a register are compared with the contents of the memory addressed by the tde register, the contents of the tde register are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is a mismatch, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the a register or of the memory addressed by the tde register. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpme
449 chapter 7 description of instructions cmpme acknowledgeable interrupt or macro service request? yes no z = 0? s, z, ac, p/v, cy (tde) ?a tde tde 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
450 chapter 7 description of instructions [coding example] mov c, #20h movg tde, #56283h mov a, #00h cmpme [tde +], a ; indicates whether the 20h-byte data from address 56283h is all 00h bnz $jmp ; branches to address jmp if there is data that is not 00h c byte tde 0 7 a register end of execution yes yes =? no =? =? yes yes no no end of execution
451 chapter 7 description of instructions compare multiple not equal byte block comparison with fixed byte data (mismatch detection) [instruction format] cmpmne [tde + ], a cmpmne [tde C ], a [operation] (tde) C a, tde tde + 1, c c C 1 end if c = 0 or z = 1 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or z = 1 [operands] mnemonic operands cmpmne [tde + ], a [tde C ], a [flags] s z ac p/v cy v [description] ? the contents of the a register are compared with the contents of the memory addressed by the tde register, the contents of the tde register are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is a match or the contents of the c register are 0. ? execution of this instruction does not change the contents of the a register or of the memory addressed by the tde register. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpmne
452 chapter 7 description of instructions cmpmne acknowledgeable interrupt or macro service request? yes no z = 1? s, z, ac, p/v, cy (tde) ?a tde tde 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
453 chapter 7 description of instructions [coding example] mov c, #00h ; c 00h movg tde, #3000h ; tde 3000h cmpmne [tde +], a bz $imp ; branches to the address indicated by label imp if the same value as that of the a register is in 3000h to 30ffh c byte tde 0 7 a register end of execution yes yes ? no ? ? yes yes no no end of execution
454 chapter 7 description of instructions compare multiple carry byte block comparison with fixed byte data (size comparison) [instruction format] cmpmc [tde + ], a cmpmc [tde C ], a [operation] (tde) C a, tde tde + 1, c c C 1 end if c = 0 or cy = 0 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or cy = 0 [operands] mnemonic operands cmpmc [tde + ], a [tde C ], a [flags] s z ac p/v cy v [description] ? the contents of the a register are compared with the contents of the memory addressed by the tde register, the contents of the tde register are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is that the contents of the memory addressed by the tde register are equal to or greater than the contents of the a register, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the a register or of the memory addressed by the tde register. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpmc
455 chapter 7 description of instructions cmpmc acknowledgeable interrupt or macro service request? yes no cy = 0? s, z, ac, p/v, cy (tde) ?a tde tde 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
456 chapter 7 description of instructions [coding example] mov c, #10h mov a, #80h movg tde, #567800h cmpmc [tde +], a bnc $big ; branches to address big if data of 80h or above is present in the 10h-byte data from address 567800h c byte tde 0 7 a register end of execution yes yes 457 chapter 7 description of instructions compare multiple not carry byte block comparison with fixed byte data (size comparison) [instruction format] cmpmnc [tde + ], a cmpmnc [tde C ], a [operation] (tde) C a, tde tde + 1, c c C 1 end if c = 0 or cy = 1 (tde) C a, tde tde C 1, c c C 1 end if c = 0 or cy = 1 [operands] mnemonic operands cmpmnc [tde + ], a [tde C ], a [flags] s z ac p/v cy v [description] ? the contents of the a register are compared with the contents of the memory addressed by the tde register, the contents of the tde register are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is that the contents of the a register are greater, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the a register or of the memory addressed by the tde register. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpmnc
458 chapter 7 description of instructions cmpmnc acknowledgeable interrupt or macro service request? yes no cy = 1? s, z, ac, p/v, cy (tde) ?a tde tde 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
459 chapter 7 description of instructions [coding example] mov c, #00h ; c 00h movg tde, #8000h ; tde 8000h cmpmnc [tde +], a bc $jmp ; branches to the address indicated by label jmp if there is a value greater than the contents of the a register in 8000h to 80ffh c byte tde 0 7 a register end of execution yes yes ? 3 no 3 ? 3 ? yes yes no no end of execution
460 chapter 7 description of instructions compare block equal byte block comparison with byte data (match detection) [instruction format] cmpbke [tde + ], [whl + ] cmpbke [tde C ], [whl C ] [operation] (tde) C (whl), tde tde + 1, whl whl + 1, c c C 1 end if c = 0 or z = 0 (tde) C (whl), tde tde C 1, whl whl C 1, c c C 1 end if c = 0 or z = 0 [operands] mnemonic operands cmpbke [tde + ], [whl + ] [tde C ], [whl C ] [flags] s z ac p/v cy v [description] ? the contents of the memory addressed by the whl register are compared with the contents of the memory addressed by the tde register, the contents of the tde and whl registers are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is a mismatch, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the memory addressed by the tde and whl registers. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde, whl, and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpbke
461 chapter 7 description of instructions cmpbke acknowledgeable interrupt or macro service request? yes no z = 0? s, z, ac, p/v, cy (tde) ?(whl) tde tde 1 note whl whl 1 note c c? end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
462 chapter 7 description of instructions [coding example] mov c, #40h movg tde, #342156h movg whl, #3421aah cmpbke [tde +], [whl +] bne $diff ; compares the 40h-byte data from address 342156h with the data from address 3421aah, and branches to address diff if there is different data c byte whl 0 7 end of execution yes yes =? no =? =? yes yes no no end of execution tde
463 chapter 7 description of instructions compare block not equal byte block comparison with byte data (mismatch detection) [instruction format] cmpbkne [tde + ], [whl + ] cmpbkne [tde C ], [whl C ] [operation] (tde) C (whl), tde tde + 1, whl whl + 1, c c C 1 end if c = 0 or z = 1 (tde) C (whl), tde tde C 1, whl whl C 1, c c C 1 end if c = 0 or z = 1 [operands] mnemonic operands cmpbkne [tde + ], [whl + ] [tde C ], [whl C ] [flags] s z ac p/v cy v [description] ? the contents of the memory addressed by the whl register are compared with the contents of the memory addressed by the tde register, the contents of the tde and whl registers are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is a match, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the memory addressed by the tde and whl registers. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde, whl, and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpbkne
464 chapter 7 description of instructions cmpbkne acknowledgeable interrupt or macro service request? yes no z = 1? s, z, ac, p/v, cy (tde) ?(whl) tde tde 1 note whl whl 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
465 chapter 7 description of instructions [coding example] mov c, #5h movg tde, #0ffc50h movg whl, #0fc50h cmpbkne [tde +], [whl +] be $find ; compares the 5-byte data from address 0ffc50h with the data from address 0fc50h, and branches to address find if there is matching data c byte whl 0 7 end of execution yes yes ? no ? ? yes yes no no end of execution tde
466 chapter 7 description of instructions compare block carry byte block comparison with byte data (size detection) [instruction format] cmpbkc [tde + ], [whl + ] cmpbkc [tde C ], [whl C ] [operation] (tde) C (whl), tde tde + 1, whl whl + 1, c c C 1 end if c = 0 or cy = 0 (tde) C (whl), tde tde C 1, whl whl C 1, c c C 1 end if c = 0 or cy = 0 [operands] mnemonic operands cmpbkc [tde + ], [whl + ] [tde C ], [whl C ] [flags] s z ac p/v cy v [description] ? the contents of the memory addressed by the whl register are compared with the contents of the memory addressed by the tde register, the contents of the tde and whl registers are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is that the contents of the memory addressed by the tde register are equal to or greater than the contents of the memory addressed by the whl register, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the memory addressed by the tde and whl registers. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde, whl, and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpbkc
467 chapter 7 description of instructions cmpbkc acknowledgeable interrupt or macro service request? yes no cy = 0? s, z, ac, p/v, cy (tde) ?(whl) tde tde 1 note whl whl 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
468 chapter 7 description of instructions [coding example] mov c, #3h movg tde, #0e8762h movg whl, #03502h cmpbkc [tde C ], [whl C ] bnc $big ; compares the 3-byte data from address 0e8760h with the 3-byte data from address 03500h, and branches to address big if the result of the comparison is that the values are the same or the 3-byte data from address 0e8760h is greater c byte whl 0 7 end of execution yes yes 469 chapter 7 description of instructions compare block not carry byte fixed byte data block comparison (size comparison) [instruction format] cmpbknc [tde + ], [whl + ] cmpbknc [tde C ], [whl C ] [operation] (tde) C (whl), tde tde + 1, whl whl + 1, c c C 1 end if c = 0 or cy = 1 (tde) C (whl), tde tde C 1, whl whl C 1, c c C 1 end if c = 0 or cy = 1 [operands] mnemonic operands cmpbknc [tde + ], [whl + ] [tde C ], [whl C ] [flags] s z ac p/v cy v [description] ? the contents of the memory addressed by the whl register are compared with the contents of the memory addressed by the tde register, the contents of the tde and whl registers are incremented/decremented, and the contents of the c register are decremented. the above operations are repeated until the result of the comparison is that the contents of the memory addressed by the whl register are greater, or the contents of the c register are 0. ? execution of this instruction does not change the contents of the memory addressed by the tde and whl registers. ? if an acknowledgeable interrupt or macro service request is generated during execution of this instruction, execution of this instruction is interrupted and the interrupt or macro service request is acknowledged. when an interrupt is acknowledged, if the return address and the contents of the tde, whl, and c registers used by this instruction which have been saved to the stack or to rp2 and r7 are not changed, execution of the interrupted instruction is resumed upon returning from the interrupt. when a macro service request is acknowledged, execution of this instruction is resumed after completion of the macro service. ? the s, z, ac, p/v, and cy flags are changed in accordance with the last compare operation (subtraction) executed by this instruction. ? the s flag is set (1) if bit 7 is set (1) as a result of the subtraction, and cleared (0) otherwise. ? the z flag is set (1) if the result of the subtraction is 0, and z flag is cleared (0) otherwise. ? the ac flag is set (1) if a borrow is generated out of bit 4 into bit 3 as a result of the subtraction, and cleared (0) otherwise. ? the p/v flag is set (1) if a borrow is generated in bit 6 and a borrow is not generated in bit 7 as a result of the subtraction (when underflow is generated by a twos complement type operation), or if a borrow is not generated in bit 6 and a borrow is generated in bit 7 (when overflow is generated by a twos complement type operation), and is cleared (0) otherwise. ? the cy flag is set (1) if a borrow is generated in bit 7 as a result of the subtraction, and cleared (0) otherwise. cmpbknc
470 chapter 7 description of instructions cmpbknc acknowledgeable interrupt or macro service request? yes no cy = 1? s, z, ac, p/v, cy (tde) ?(whl) tde tde 1 note whl whl 1 note c c ?1 end c = 0? yes adjust pc value to enable instruction restart to interrupt or macro service processing yes no note +1 if the operand specifies "+", and ? if it specifies "? no
471 chapter 7 description of instructions [coding example] mov c, #4h movg tde, #05503h movg whl, #0ffc03h cmpbknc [tde C ], [whl C ] bc $little ; compares the 4-byte data from address 05500h with the data from address 0ffc00h, and branches to address little if the data from address 05500h is smaller ? ? ? c byte whl 0 7 end of execution yes yes no yes yes no no end of execution tde
472 [memo]
473 chapter 8 development tools tools required for 78k/iv series product development are shown in this chapter. for details, refer to the users manual hardware of each device and the single-chip microcontroller development tool selection guide (u11069e) .
474 chapter 8 development tools 8.1 development tools the following development tools are provided to develop programs for application systems table 8-1. types and functions of development tools (1/2) development tools functions hardware in-circuit emulator this is a hardware tool used for program debugging for system development (ie-784000-r) of 78k/iv series. (ie-78k4-ns) when a personal computer (pc-9800 series or ibm pc/(ie-78k4-ns) at tm ) is used as a host machine of this emulator, it is possible to perform more efficient debugging by means of functions such as the symbolic debugging and the object file and symbol file transfer. an on-chip serial interface rs-232-c enables connection to a prom programmer (pg-1500). emulation board this is a board to emulate peripheral hardware that is specific to the target (ie-78 -r-em) device. (ie-78 -r-em-a) (ie-78 -r-em) i/o emulation board this is a board to emulate peripheral hardware that is specific to the target (ie-78 -r-em1) device. it is used in combination with an emulation board. the i/o emulation (ie-78 -r-em1) board required for the target device depends on the products. (ie-78 -ns-em1) emulation probe this probe connects the in-circuit emulator to the target device. it is provided (ep-78 ......) each target device package. (np- ......) conversion socket this is a socket used to connect the emulation probe for qfp to the (ev-9200 - ) application system. it is a standard accessory for an emulation probe for qpf. mount it on the circuit board for an application system. programmer adapter this is an adapter for the prom programmer (pg-1500) that is used for (pa-78p ......) programming on-chip prom products. jig (ev-9900) jig for removing wqfp-package product from the ev-9200 - .
475 chapter 8 development tools table 8-1. types and functions of development tools (2/2) development tools functions software integrated debugger this is a control program for in-circuit emulators for the 78k/iv series. this (id78k4) debugger is used in combination with the device files. this debugger enables more effective debugging than previous ie controllers by offering the following features: source program level debugging written in c language, structured assembly language, or assembly language and display for a variety of simultaneous a variety of information by dividing the screen of the host machine. device file used in combination with an integrated debugger. this file is required when debugging the 78k/iv series. in-circuit emulator control this is software to perform efficient debugging by connecting the ie to the program (ie controller) host machine. this software makes full use of the capabilities of the ie by means of file (object or symbol) transfer, on-line assembly, disassembly, break condition (event) setup, etc. relocatable assembler note 1 this is a program to convert a program written in mnemonic to an object code that can be executed by microcontrollers. in addition, an automatic function to perform a symbol table creation and branch instruction optimization processing is provided. structured assembler this software introduces a structured programming method into the preprocessor assembler. it enables writing functions with a c language-like control structure without sacrificing the size and speed of the assembler. c compiler note 1 this is a program that translates a program written in the high-level c language into object code, which can be executed by a microcontroller. c library source this source program is attached to the c compiler. this program is required when modifying a library (to better match user specifications). system simulator this is a software development support tool. c source level or assembler (sm78k4) note 2 level debugging is possible while simulating the operation of the target system in the host machine. the sm78k4 enables the verification of the logic and performance of applications independently from the hardware development. consequently, development efficiency and software quality can be improved. notes 1. used in combination with the device files for 78k/iv series. 2. used in combination with the device files. remark all the software listed above runs under ms-dos tm and pc dos tm .
476 chapter 8 development tools figure 8-1. development tools structure (on-chip prom) (on-chip flash memory) notes 1. integrated debugger and device file 2. conversion socket to connect emulation probe to the target system (products whose prefix is ev-9200) remark the meaning of part number prefix are as follows. ie : in-circuit emulator ep : emulation probe np : emulation probe (made by naitou densei machidaseisakusho, co., ltd.) pa : prom programmer adapter fa : adapter for flash memory writing ...... : varies depending on the target device or package. host machine pc-9800 series or ibm pc/at note 1 ie-784000-r ie-78k4-ns break board emulation board in-circuit emulator prom programmer pg-1500 pa-78p .......... programmer adapter on-chip prom product pd78p emulation probe ep-78 .......... np- .......... target system real-time os relocatable assembler, structured assembler, c compiler note 2 m note 1 ie-784000-r ie-78k4-ns emulation board in-circuit emulator flash memory writing tool flashpro ii (fl-pr2) fa- on-chip flash memory product pd78f emulation probe ep-78 .......... np- .......... target system real-time os relocatable assembler, structured assembler, c compiler note 2 host machine pc-9800 series or ibm pc/at m
477 chapter 8 development tools 8.2 prom programming tools (1) hardware pg-1500 prom programmer which allows programming, in standalone mode or via operation from a host machine, of a single-chip microcontroller with on-chip prom by connection of the board provided and a separately available prom programmer adapter. it can also program typical 256-kbit to 4- mbit prom. prom programmer adapter adapter which provided for each product with on-chip prom. this adapter is used in combination with prom programmer. for actual product names, refer to the users manual hardware for the relevant device. (2) software pg-1500 controller controls the pg-1500 on the host machine by connecting pg-1500 to the host machine with parallel and serial interface.
478 chapter 8 development tools 8.3 flash memory programming tools flashpro ii (fl-pr2) this is flash programmer for a microcontroller in the flash memory. adapter for flash memory this must be wired to match the objective product. programming for details about part names, refer to the hardware version of the users manual for each device. remark this is a product of naitou densei machidaseisakusho co., ltd. consult with an nec representative before buying this part.
479 rx78k/iv note the aim of the rx78k/iv is to realize multi-task environments for real-time required control fields. the cpu idle time can be allotted to other processes to improve the overall performance of the system. the rx78k/iv provides system calls (31 kinds) conforming to the m itron specification, and the tools (configurator) for creating the rx78k/iv nucleus and several information tables. the rx78k/iv should be used in combination with separately available assembler package (ra78k4) and device files. real-time os is a dos-based application. when using this application on windows, use the dos prompt. mx78k4 m itron specification subset os. nucleus of mx78k4 is attached. task, event, and time management are performed. task execution sequence is controlled in task management and with subsequent switch to the next execution task. mx78k4 is a dos-based application. when using this application on windows, use the dos prompt. note when purchasing the rx78k/iv, the purchasing application must be filled in advance and a using conditions agreement signed. chapter 9 embedded software 9.1 real-time os real-time os os
480 [memo]
481 appendix a index of instructions (mnemonics: by function) [8-bit data transfer instruction] mov ................................................................... 294 [16-bit data transfer instruction] movw ................................................................ 297 [24-bit data transfer instruction] movg ................................................................ 300 [8-bit data exchange instruction] xch .................................................................... 302 [16-bit data exchange instruction] xchw ................................................................ 304 [8-bit operation instructions] add .................................................................... 306 addc ................................................................. 307 sub .................................................................... 308 subc ................................................................. 309 cmp ................................................................... 310 and .................................................................... 312 or ...................................................................... 313 xor ................................................................... 314 [16-bit operation instructions] addw ................................................................ 316 subw ................................................................ 318 cmpw ................................................................ 320 [24-bit operation instructions] addg ................................................................. 323 subg ................................................................. 324 [multiplication/division instructions] mulu ................................................................. 326 muluw .............................................................. 327 mulw ................................................................ 328 divuw ............................................................... 329 divux ................................................................ 330 [special operation instructions] macw ................................................................ 332 macsw ............................................................. 335 sacw ................................................................ 338 [increment/decrement instructions] inc ..................................................................... 342 dec .................................................................... 343 incw .................................................................. 344 decw ................................................................ 345 incg .................................................................. 346 decg ................................................................. 347 [adjustment instructions] adjba ................................................................ 349 adjbs ................................................................ 350 cvtbw .............................................................. 351 [shift/rotate instructions] ror ................................................................... 353 rol .................................................................... 354 rorc ................................................................. 355 rolc ................................................................. 356 shr .................................................................... 357 shl .................................................................... 358 shrw ................................................................ 359 shlw ................................................................. 360 ror4 ................................................................. 361 rol4 .................................................................. 362
482 appendix a index of instructions (mnemonics: by function) [bit manipulation instructions] mov1 ................................................................. 364 and1 .................................................................. 366 or1 .................................................................... 368 xor1 ................................................................. 370 not1 .................................................................. 371 set1 .................................................................. 372 clr1 .................................................................. 373 [stack manipulation instructions] push ................................................................. 375 pushu ............................................................... 377 pop .................................................................... 378 popu ................................................................. 380 movg ................................................................ 381 addwg ............................................................. 382 subwg .............................................................. 383 incg sp ............................................................ 384 decg sp ........................................................... 385 [call/return instructions] call .................................................................. 387 callf ................................................................ 388 callt ................................................................ 389 brk .................................................................... 390 brkcs ............................................................... 391 ret .................................................................... 393 reti ................................................................... 394 retb .................................................................. 395 retcs ............................................................... 396 retcsb ............................................................ 398 [unconditional branch instruction] br ...................................................................... 401 [conditional branch instructions] bnz .................................................................... 403 bne .................................................................... 403 bz ....................................................................... 404 be ...................................................................... 404 bnc .................................................................... 405 bnl .................................................................... 405 bc ...................................................................... 406 bl ....................................................................... 406 bnv .................................................................... 407 bpo .................................................................... 407 bv ...................................................................... 408 bpe .................................................................... 408 bp ...................................................................... 409 bn ...................................................................... 410 blt ..................................................................... 411 bge .................................................................... 412 ble .................................................................... 413 bgt .................................................................... 414 bnh .................................................................... 415 bh ...................................................................... 416 bf ....................................................................... 417 bt ....................................................................... 418 btclr ............................................................... 419 bfset ................................................................ 420 dbnz ................................................................. 421 [cpu control instructions] mov stbc, #byte ............................................. 423 mov wdm, #byte ............................................. 424 location ......................................................... 425 sel rbn ............................................................ 426 sel rbn, alt ................................................... 427 swrs ................................................................ 428 nop ................................................................... 429 ei ........................................................................ 430 di ........................................................................ 431 [special instructions] chkl .................................................................. 433 chkla ............................................................... 434
483 appendix a index of instructions (mnemonics: by function) [string instructions] movtblw ......................................................... 436 movm ................................................................ 438 xchm ................................................................. 440 movbk .............................................................. 442 xchbk ............................................................... 445 cmpme .............................................................. 448 cmpmne ........................................................... 451 cmpmc .............................................................. 454 cmpmnc ........................................................... 457 cmpbke ............................................................ 460 cmpbkne ......................................................... 463 cmpbkc ............................................................ 466 cmpbknc ......................................................... 469
484 [memo]
485 appendix b index of instructions (mnemonics: alphabetical order) [a] add ................................................................... 306 addc ................................................................ 307 addg ................................................................ 323 addw ............................................................... 316 addwg ............................................................ 382 adjba ............................................................... 349 adjbs ............................................................... 350 and ................................................................... 312 and1 ................................................................. 366 [b] bc ..................................................................... 406 be ...................................................................... 404 bf ...................................................................... 417 bfset ............................................................... 420 bge ................................................................... 412 bgt ................................................................... 414 bh ..................................................................... 416 bl ...................................................................... 406 ble .................................................................... 413 blt .................................................................... 411 bn ..................................................................... 410 bnc ................................................................... 405 bne ................................................................... 403 bnh ................................................................... 415 bnl ................................................................... 405 bnv ................................................................... 407 bnz ................................................................... 403 bp ...................................................................... 409 bpe ................................................................... 408 bpo ................................................................... 407 br ..................................................................... 401 brk ................................................................... 390 brkcs .............................................................. 391 bt ...................................................................... 418 btclr .............................................................. 419 bv ...................................................................... 408 bz ...................................................................... 404 [c] call ................................................................. 387 callf ............................................................... 388 callt ............................................................... 389 chkl ................................................................. 433 chkla .............................................................. 434 clr1 ................................................................. 373 cmp .................................................................. 310 cmpbkc ........................................................... 466 cmpbke ........................................................... 460 cmpbknc ........................................................ 469 cmpbkne ........................................................ 463 cmpmc ............................................................. 454 cmpme ............................................................. 448 cmpmnc .......................................................... 457 cmpmne .......................................................... 451 cmpw ............................................................... 320 cvtbw ............................................................. 351 [d] dbnz ................................................................. 421 dec ................................................................... 343 decg ................................................................ 347 decg sp .......................................................... 385 decw ............................................................... 345 di ....................................................................... 431 divuw .............................................................. 329 divux ............................................................... 330 [e] ei ....................................................................... 430 [i] inc .................................................................... 342 incg ................................................................. 346 incg sp ........................................................... 384 incw ................................................................. 344
486 appendix b index of instructions (mnemonics: alphabetical order) [l] location ........................................................ 425 [m] macsw ............................................................ 335 macw ............................................................... 332 mov .................................................................. 294 movbk ............................................................. 442 movg ....................................................... 300, 381 movm ............................................................... 297 mov stbc, #byte ............................................ 423 movtblw ........................................................ 436 movw ............................................................... 438 mov wdm, #byte ............................................ 424 mov1 ................................................................ 364 mulu ................................................................ 326 muluw ............................................................. 327 mulw ............................................................... 328 [n] nop ................................................................... 429 not1 ................................................................. 371 [o] or ..................................................................... 313 or1 ................................................................... 368 [p] pop ................................................................... 378 popu ................................................................ 380 push ................................................................ 375 pushu .............................................................. 377 [r] rol ................................................................... 354 rolc ................................................................ 356 rol4 ................................................................. 362 ror .................................................................. 353 rorc ................................................................ 355 ror4 ................................................................ 361 ret ................................................................... 393 retb ................................................................. 395 retcs .............................................................. 396 retcsb ............................................................ 398 reti .................................................................. 394 [s] sacw ............................................................... 338 sel rbn ........................................................... 426 sel rbn, alt .................................................. 427 set1 ................................................................. 372 shl ................................................................... 358 shlw ................................................................ 360 shr ................................................................... 357 shrw ............................................................... 359 sub ................................................................... 308 subc ................................................................ 309 subg ................................................................ 324 subw ............................................................... 318 subwg ............................................................. 383 swrs ............................................................... 428 [x] xch ................................................................... 302 xchbk .............................................................. 445 xchm ................................................................ 440 xchw ............................................................... 304 xor ................................................................... 314 xor1 ................................................................ 370
487 appendix c revision history revisions through this document are listed in the following table. the column "applicable chapters" indicates the chapters in each edition. edition major revisions from previous edition applicable chapters 2nd edition ? the following instructions are added to bit manipulation instructions. chapter 6 mov1 cy, !addr16.bit instruction set cy, !!addr24, bit !addr16.bit, cy !!addr24.bit, cy and1, or1 cy, !addr16.bit cy, !!addr24.bit cy,/!addr16.bit cy,/!!addr24.bit xor1 cy, !addr16.bit cy,!!addr24.bit not1, set1, clr1 !addr16.bit !!addr24.bit ? the following instructions are added to conditional branch instructions. bf, bt, bfset, btclr !addr16.bit, $addr20 !!addr24.bit, $addr20 3rd edition ? descriptions regarding m pd784915 subseries are added. throughout ? m pd784020 is added to m pd784026 subseries. notation used in section 5.2.10 short direct 24-bit memory indirect chapter 5 addressing addressing changed as follows: [%saddrp] ? [%saddrg] ? saddrg1 and saddrg2 are added to section 6.1 legend, (1) operand chapter 6 identifiers and description (2/2). instruction set ? movg operand corrected as follows: [tde+hl], whl ? [tde+c], whl ? section 6.5 number of instruction clocks is added ? 3.5-inch 2hc or 3.5-inch 2hd is added as supply medium for ibm pc/at chapter 8 ? part numbers for ordering integrated debuggers are changed as follows: development tools m s5a10id78k4 ? m saa10id78k4 m s5a13id78k4 ? m saa13id78k4 m s7b10id78k4 ? m sbb10id78k4 (1/3)
488 appendix c revision history edition major revisions from previous edition applicable chapters 4th edition ? gk package (80-pin plastic tqfp, fine pitch, 12 mm 12 mm) is added throughout to m pd784021. ? descriptions regarding m pd784038/784038y subseries are added. ? descriptions regarding m pd784046 subseries are added. ? descriptions regarding m pd784208/784208y subseries are added. ? a note mark is appended to the retcs instruction, which indicates that the m pd784208 and 784208y subseries do not have the retcs instruction. ? descriptions regarding flash memory are added. chapter 8 development tools ? descriptions regarding the mx78k4 are added. chapter 9 software for embedding 5th edition ? new products ( m pd784031/y) and new package (80-pin plastic qfp throughout (14 mm square, 1.4 mm thick)) have been added to the m pd784038/y subseries. ? entries related to the new product ( m pd784054) of the m pd784046 subseries have been added. ? entries related to the m pd784208 subseries have been deleted. ? entries related to the m pd784216/y subseries have been added. ? entries related to the new products ( m pd784915a, 784916a) of the m pd784915 subseries have been added. ? entries related to the m pd784908 subseries have been added. ? entries related to the m pd78f4943 subseries have been added. ? note that there is no retcs instruction in the m pd764208 and chapter 6 m pd784208y subseries has been deleted. instruction set ? the entry, highest-order/on highest-order side for reti instructions chapter 7 has been changed to highest priority. description of ? note that there is no retcs instruction in the m pd764208 and instructions m pd784208y subseries has been deleted, target has been added to the instruction format, and the entry, highest-order/on highest-order side has been changed to highest priority. ? target has been added to the instruction format for retcsb instructions. ? entries related to flash memory have been corrected. chapter 8 development tools (2/3)
489 appendix c revision history edition major revisions from previous edition applicable chapters 6th edition ? adds the m pd784218, 784218y, 784225, 784225y, 784928, and throughout 784928y subseries and m pd784943. ? the following products are in the development to completion stage: m pd784037, 784038, 78p4038 m pd784031y, 784035y, 784036y, 784037y, 784038y, 78p4038y m pd784215, 784216 m pd784215y, 784216y m pd784915a, 784916a ? changes the gc-7ea package to the gc-8eu package in the m pd784214, 784215, 784216, 784214y, 784215y, and 784216y. ? describes that the m pd784915 subseries provide the fixed location 0 instruction instead of the location 0fh instruction. ? adds note describing that the special instructions (chkl and chkla) are not available for the m pd784216, 784216y, 784218, 784218y, 784225, and 784215y, ? changes the m pd78f4943 subseries to the m pd784943 subseries. 7th edition ? addition of m pd784937 and 784955 subseries. deletion of m pd784943. throughout ? the following products changed from under development stage to completed. m pd784031(a), 784035(a), 784036(a), m pd784044(a), 784044(a1), 784044(a2), 784046(a), 784046(a1), 784046(a2), m pd784054(a), 784054(a1), 784054(a2), m pd784214, 784214y, m pd784915b, 784916b, m pd784927, 78f4928, 784927y, 78f4928y ? modification of gc-7ea package to gc-8eu package for the m pd78f4216, 78f4216y ? modification of power supply voltage in the m pd784908 subseries. mask rom version ( m pd784907, 784908) ... changed from (v dd = 4.5 to 5.5 v) to (v dd = 3.5 to 5.5 v) prom version ( m pd78p4908) ... changed from (v dd = 4.5 to 5.5 v) to (v dd = 4.0 to 5.5 v) modification of the notes in the special instructions (chkl, chkla). chapter 6 instruction set modification of the operation sequence of the pop instruction. chapter 7 addition of the note in chkl instruction. description of addition of note in chkla instruction. instructions modification of the format. chapter 8 development tools addition of the description on the pc environment. chapter 9 embedded software (3/3)
490 [memo]
although nec has taken all possible steps to ensure that the documentation supplied to our customers is complete, bug free and up-to-date, we readily accept that errors may occur. despite all the care and precautions we've taken, you may encounter problems in the documentation. please complete this form whenever you'd like to report errors or suggest improvements to us. hong kong, philippines, oceania nec electronics hong kong ltd. fax: +852-2886-9022/9044 korea nec electronics hong kong ltd. seoul branch fax: 02-528-4411 taiwan nec electronics taiwan ltd. fax: 02-719-5951 address north america nec electronics inc. corporate communications dept. fax: 1-800-729-9288 1-408-588-6130 europe nec electronics (europe) gmbh technical documentation dept. fax: +49-211-6503-274 south america nec do brasil s.a. fax: +55-11-6465-6829 asian nations except philippines nec electronics singapore pte. ltd. fax: +65-250-3583 japan nec semiconductor technical hotline fax: 044-548-7900 i would like to report the following error/make the following suggestion: document title: document number: page number: thank you for your kind support. if possible, please fax the referenced page or drawing. excellent good acceptable poor document rating clarity technical accuracy organization cs 98.2 name company from: tel. fax facsimile message

▲Up To Search▲

Price & Availability of PD784224Y

	To Download PD784224Y Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .